NJU6673 データシートの表示（PDF） - Japan Radio Corporation
部品番号
コンポーネント説明
メーカー
NJU6673 Datasheet PDF : 38 Pages
| |||
NJU6673
TERMINAL DESCRIPTION
No.
1,
2,
21-
24,
33,
37,
38,
57,
76,
77,
79,
80,
97,
198,
210,
211
4,5,6,
54-56
9-11,
34-36
73-75
70-72
67-69
64-66
61-63
39-41
42-44
45-47
48-50
51-53
58-60
13
12
Symbol
DUMMY1
DUMMY2
DUMMY3 -
DUMMY6
DUMMY7
DUMMY8
DUMMY9
DUMMY10
DUMMY11
DUMMY12
DUMMY13
DUMMY14
DUMMY15
DUMMY16
DUMMY17
DUMMY18
VDD
VSS
I/O
Function
Dummy Terminal.
These are open terminals electrically.
Power Power supply terminal. (+2.4 to +5.5V)
GND Ground terminal. (0V)
V1
V2
V3
V4
V5
C1+
C1-
C2+
C2-
VOUT
VR
T1,
T2
Power
O
LCD Driving Voltage Supplying Terminals.
In case of external power supply operation without internal power supply
operation, each level of LCD driving voltage is supplied from outside
fitting with following relation.
VDD≥V1≥V2≥V3≥V4≥V5≥VOUT
In case of internal power supply, LCD driving voltages V1 to V4
depending on the bias selection are supplied as shown in follows;
Duty
Bias
V1
V2
V3
V4
1/15 Duty 1/5 Bias V5+4/5 VLCD V5+3/5 VLCD V5+2/5 VLCD V5+1/5 VLCD
1/25 Duty 1/6 Bias V5+5/6 VLCD V5+4/6 VLCD V5+2/6 VLCD V5+1/6 VLCD
VLCD=VDD-V5
Condenser connecting terminals for internal Voltage Booster.
Boosting time is selected by each connected condenser.
In case of 3-time boost operation, connect the condenser between C1+
and C1-, C2+ and C2-.
In case of 2-time boost operation, connect the condenser between C2+
and C2-, connect C2+ to C1+, and C1- should be open.
O Boosted voltage output terminal. Connects the capacitor between VOUT
terminal and VSS.
I VLCD voltage adjustment terminal. The gain of VLCD setup circuit for V5
level is adjusted by external resistor.
I LCD bias voltage control terminals.
T1
T2
Voltage
booster circuit
Voltage adjustor
V/F circuit
L H/L
Available
Available
Available
H L Not available
Available
Available
H H Not available Not available
Available
25
D0
I/O Data input / output terminals.
26
D1
In parallel interface Mode (P/S=”H”)
27
D2
I/O terminals of 8-bit bus.
28
D3
In Serial interface Mode(P/S=”L”)
29
D4
D7:Input terminal of serial data (SI).
30
D5
D6:Input terminal of serial data clock (SCL).
31
D6(SCL)
D5 to D0 terminals are High impedance.
32
D7(SI)
When CS=”H” , D0 to D7 terminals are high-impedance.
Ver.2003-04-08
-7-
Share Link: 