NJW1143 データシートの表示（PDF） - Japan Radio Corporation
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NJW1143 Datasheet PDF : 17 Pages
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NJW1143
s DEFINITION OF I2C REGISTER
q I2C BUS FORMAT
MSB
LSB MSB
LSB MSB
S Slave Address A Select Address A
1bit
8bit
1bit
8bit
1bit
S: Starting Term
A: Acknowledge Bit
P: Ending Term
q SLAVE ADDRESS
MSB
1
0
0
0
0
ADR1 ADR0
Data
8bit
LSB
R/W
LSB
AP
1bit 1bit
ADR0, ADR1: Hardware pin programmable address bits
80(h), 82(h), 84(h), 86(h)
R/W=0: Write mode for register setting
R/W=1: Not available
q CONTROL REGISTER TABLE
The select address sets each function (Volume, Balance, AGC, Tone Control, Surround etc.).
The auto-increment function cycles the select address as follows.
00H→01H→02H→03H→00H
Select
Address
D7
D6
00H
01H
CHS
02H
BCB
03H
BCT
BIT
D5
D4
D3
VOL
BAL
BASS
TREB
D2
D1
D0
AGC-SW
Don’t Care
SUR
AGC-FLAT
AUX1
AUX0
q CONTROL REGISTER DEFAULT VALUE
Control register default value is all “0”.
Select
BIT
Address
D7
D6
D5
D4
D3
D2
D1
D0
00H
0
0
0
0
0
0
0
0
01H
0
0
0
0
0
0
0
0
02H
0
0
0
0
0
0
0
0
03H
0
0
0
0
0
0
0
0
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