NM27C020 データシートの表示（PDF） - Fairchild Semiconductor

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NM27C020

2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

Fairchild Semiconductor 

Capacitance TA = +25°C, f = 1 MHz (Note 5)

Symbol Parameter

Conditions Typ

CIN

Input Capacitance

VIN = 0V

9

COUT

Output Capacitance VOUT = 0V

12

Max

15

15

Units

pF

pF

AC Test Conditions

Output Load

1 TTL Gate and CL = 100 pF (Note 11)

Input Rise and Fall Times

≤5 ns

Input Pulse Levels

0.45V to 2.4V

Timing Measurement Reference Level (Note 13)

Inputs

0.8V and 2V

Outputs

0.8V and 2V

AC Waveforms (Notes 9, 10, 12)

ADDRESS

2V

0.8V

Address Valid

CE

2V

0.8V

2V

OE

0.8V

2V

OUTPUT

0.8V

tCE

Hi-Z

tACC

(Note 6)

tOE

(Note 6)

Valid Output

tCF

(Note 7, 8)

tDF

(Note 7, 8)

tOH

Hi-Z

DS010835-4

Note 5: This parameter is only sampled and is not 100% tested.

Note 6: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC.

Note 7: The tDF and tCF compare level is determined as follows:

High to TRI-STATE®, the measured VOH1 (DC) - 0.10V;

Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.

Note 8: TRI-STATE may be attained using OE or CE .

Note 9: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 MF ceramic capacitor be used on every

device between VCC and GND.

Note 10: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.

Note 11: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA.

CL: 100 pF includes fixture capacitance.

Note 12: VPP may be connected to VCC except during programming.

Note 13: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

6

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