NM93C56VMT8 データシートの表示（PDF） - Fairchild Semiconductor

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NM93C56VMT8

(MICROWIRE™ Bus Interface) 2048-Bit Serial EEPROM with Data Protect and Sequential Read

Fairchild Semiconductor 

Absolute Maximum Ratings (Note 1)

Operating Conditions

Ambient Storage Temperature

All Input or Output Voltages

with Respect to Ground

Lead Temperature

(Soldering, 10 sec.)

ESD rating

-65°C to +150°C

+6.5V to -0.3V

+300°C

2000V

Ambient Operating Temperature

NM93CS56L/LZ

NM93CS56LE/LZE

NM93CS56LV/LZV

Power Supply (VCC)

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

2.7V to 5.5V

DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified

Symbol

Parameter

Conditions

Min

Max

Units

ICCA

ICCS

IIL

IOL

VIL

VIH

VOL

VOH

fSK

tSKH

tSKL

tSKS

tCS

tCSS

tPRES

tDH

tPES

tDIS

tCSH

tPEH

tPREH

tDIH

tPD

tSV

tDF

tWP

Operating Current

Standby Current

L

LZ (2.7V to 4.5V)

Input Leakage

Output Leakage

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

SK Clock Frequency

SK High Time

SK Low Time

SK Setup Time

Minimum CS Low Time

CS Setup Time

PRE Setup Time

DO Hold Time

PE Setup Time

DI Setup Time

CS Hold Time

PE Hold Time

PRE Hold Time

DI Hold Time

Output Delay

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

CS = VIH, SK=1.0 MHz

CS = VIL

VIN = 0V to VCC

(Note 2)

IOL = 10µA

IOH = -10µA

(Note 3)

(Note 4)

CS = VIL

1

mA

10

µA

1

µA

±1

µA

-0.1

0.8VCC

0.9VCC

0

1

1

0.2

0.15VCC

VCC +1

0.1VCC

250

V

V

KHz

µs

µs

µs

1

µs

0.2

µs

50

ns

70

ns

50

ns

0.4

µs

0

ns

250

ns

50

ns

0.4

µs

2

µs

1

µs

0.4

µs

15

ms

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage

Capacitance T = 25°C, f = 1 MHz (Note 5) to the device. This is a stress rating only and functional operation of the device at these or any other

A

conditions above those indicated in the operational sections of the specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect device reliability.

Symbol

Test

Typ Max Units Note 2: Typical leakage values are in the 20nA range.

COUT

CIN

Output Capacitance

Input Capacitance

5

pF

Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter). Maximum

SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated

5

pF

in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not

allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.

Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal

device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode

diagram on the following page.)

AC Test Conditions

Note 5: This parameter is periodically sampled and not 100% tested.

VCC Range

2.7V ≤ VCC ≤ 5.5V

(Extended Voltage Levels)

4.5V ≤ VCC ≤ 5.5V

(TTL Levels)

VIL/VIH

Input Levels

0.3V/1.8V

VIL/VIH

Timing Level

1.0V

VOL/VOH

Timing Level

0.8V/1.5V

0.4V/2.4V

1.0V/2.0V

0.4V/2.4V

Output Load: 1 TTL Gate (CL = 100 pF)

IOL/IOH

±10µA

2.1mA/-0.4mA

NM93CS56 Rev. F.2

4

www.fairchildsemi.com

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