NanoAmp Solutions, Inc.
Block Diagram (16Mb x 16)
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
13
15
13
A0-A12,
BA0, BA1
15
2
2
9
Column-Address
Counter/Latch
Bank3
Bank1 Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
(8192 x 256 x 32)
Sense Amplifiers
I/O Gating
DM Mask Logic
256
(x32)
Column
Decoder
8
COL0
1
32
32
32
Data
16
16
16
DQS
1
Generator
COL0 Input
Register
Write Mask 1
1
FIFO
&
Drivers
1
2
32 16
1
16
clk
out
clk
in
Data
16
16
DQS
1
16
CK,
COL0
CK
1
DQ0-DQ15,
LDM, UDM
LDQS,UDQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
DOC # 14-02-044 Rev A ECN # 01-1116
7
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com