SPT7824A データシートの表示（PDF） - Signal Processing Technologies
部品番号
コンポーネント説明
メーカー
SPT7824A Datasheet PDF : 11 Pages
| |||
VOLTAGE REFERENCE
The SPT7824 requires the use of two voltage references:
VFT and VFB. VFT is the force for the top of the voltage
reference ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for
the bottom of the voltage reference ladder. Both voltages are
applied across an internal reference ladder resistance of
800 ohms. The +2.5 V voltage source for reference VFT must
be current limited to 20 mA maximum if a different driving
circuit is used in place of the recommended reference circuit
shown in figures 2 and 3. In addition, there are three
reference ladder taps (VST, VRM and VSB). VST is the sense for
the top of the reference ladder (+2.0 V), VRM is the midpoint
of the ladder (0.0 V typ) and VSB is the sense for the bottom
of the reference ladder (-2.0 V). The voltages seen at VST and
VSB are the true full scale input voltages of the device when
VFT and VFB are driven to the recommended voltages (+2.5 V
and -2.5 V typical respectively). These points should be used
to monitor the actual full scale input voltage of the device and
should not be driven to the expected ideal values as is
commonly done with standard flash converters. When not
being used, a decoupling capacitor of .01 uF (chip carrier
preferred) connected to AGND from each tap is recommended
to minimize high frequency noise injection.
Figure 3 - Analog Equivalent Input Circuit
VCC
VIN
VFT
VEE
An example of a reference driver circuit recommended is
shown in figure 2. IC1 is REF-03, the +2.5 V reference with a
tolerance of 0.6% or +/- 0.015 V. The potentiometer R1 is
10 kΩ and supports a minimum adjustable range of up to
150 mV. IC2 is recommended to be an OP-07 or equivalent
device. R2 and R3 must be matched to within 0.1% with good
TC tracking to maintain a 0.3 LSB matching between VFT and
VFB. If 0.1% matching is not met, then potentiometer R4 can
be used to adjust the VFB voltage to the desired level. VFT and
VFB should be adjusted such that VST and VSB are exactly
+2.0 V and -2.0 V respectively.
The analog input range will scale proportionally with respect
to the reference voltage if a different input range is required.
The maximum scaling factor for device operation is ± 20% of
the recommended reference voltages of VFT and VFB. How-
ever, because the device is laser trimmed to optimize perfor-
mance with ± 2.5 V references, the accuracy of the device will
degrade if operated beyond a ± 2% range.
The following errors are defined:
+FS error = top of ladder offset voltage = ∆(+FS -VST+1 LSB)
-FS error = bottom of ladder offset voltage = ∆(-FS-VSB-1LSB)
where the +FS (full scale) input voltage is defined as the
output transition between 1-10 and 1-11 and the -FS input
voltage is defined as the output transition between 0-00 and
0-01.
ANALOG INPUT
VIN is the analog input. The full scale input range will be 80% of
the reference voltage or ±2 V with VFB=-2.5 V and VFT=+2.5 V.
The drive requirements for the analog inputs are minimal
when compared to conventional Flash converters due to the
SPT7824’s extremely low input capacitance of only 5 pF and
very high input resistance of 300 kΩ. For example, for an input
signal of ± 2 V p-p with an input frequency of 10 MHz, the peak
output current required for the driving circuit is only 628 µA.
CLOCK INPUT
The SPT7824 is driven from a single-ended TTL input (CLK).
The CLK pulse width (tpwH) must be kept between 10 ns and
300 ns to ensure proper operation of the internal track-and-
hold amplifier. (See timing diagram.) When operating the
SPT7824 at sampling rates above 3 MSPS, it is recom-
mended that the clock input duty cycle be kept at 50% to
optimize performance. (See figure 4.) The analog input
signal is latched on the rising edge of the CLK.
The clock input must be driven from fast TTL logic (VIH ≤4.5 V,
TRISE <6 ns). In the event the clock is driven from a high
current source, use a 100 Ω resistor in series to current limit
to approximately 45 mA.
Figure 4 - SNR vs Clock Duty Cycle
59
57
55
53
51
DCuyctyle=
tpwH
tpwL
49
tpwH tpwL
47
45
43
30
35
40
45
50
55
60
65
70
75
Duty Cycle of Positive Clock Pulse (%)
SPT
7
SPT7824
3/11/97
Share Link: 