AD7533KP データシートの表示（PDF） - Analog Devices
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AD7533KP Datasheet PDF : 13 Pages
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AD7533
OPERATION
UNIPOLAR BINARY CODE
Table 4. Unipolar Binary Operation
(2-Quadrant Multiplication)
Digital Input
Analog Output
MSB
LSB
(VOUT as shown in Figure 11)
1111111111
− VREF
⎜⎝⎛
1023
1024
⎟⎠⎞
1000000001
− VREF
⎜⎛ 513
⎝ 1024
⎟⎞
⎠
1000000000
− VREF
⎜⎝⎛
512
1024
⎟⎠⎞
=
⎜⎛ VREF
⎝2
⎟⎠⎞
0111111111
− VREF
⎜⎝⎛
511
1024
⎟⎠⎞
0000000001
− VREF
⎜⎝⎛
1
1024
⎟⎠⎞
0000000000
− VREF
⎜⎝⎛
0
1024
⎟⎠⎞
=
0
Nominal LSB magnitude for the circuit of Figure 11 is given by
LSB
= VREF
⎜⎝⎛
1
1024
⎟⎠⎞
BIPOLAR
ANALOG INPUT
±10V
VDD
R1
1kΩ
VREF
15
14
R2
RFB 330Ω
MSB
4
16
IOUT1
C1
UNIPOLAR
1
DIGITAL
INPUT LSB
13
AD7533
2
IOUT2
3
VOUT
GND
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIER.
Figure 11. Unipolar Binary Operation (2-Quadrant Multiplication)
BIPOLAR (OFFSET BINARY) CODE
Table 5. Unipolar Binary Operation
(4-Quadrant Multiplication)
Digital Input
Analog Output
MSB
LSB
(VOUT as shown in Figure 12)
1111111111
+ VREF
⎜⎝⎛
511
512
⎟⎠⎞
1000000001
+ VREF
⎜⎝⎛
1
512
⎟⎠⎞
1000000000
0
0111111111
− VREF
⎜⎝⎛
1
512
⎟⎠⎞
0000000001
− VREF
⎜⎛ 511⎟⎞
⎝ 512 ⎠
0000000000
− VREF
⎜⎝⎛
512
512
⎟⎠⎞
Nominal LSB magnitude for the circuit of Figure 12 is given by
LSB
=
VREF
⎜⎝⎛
1
512
⎟⎠⎞
BIPOLAR
ANALOG INPUT
±10V
VDD
BIPOLAR
DIGITAL
INPUT
R1
1kΩ
VREF
15
14
MSB
4
LSB
13
AD7533
3
R2
330Ω
16
IOUT1
1
2
IOUT2
C1
A1
R4
20kΩ
R3
10kΩ
R6
5kΩ
R5
20kΩ
A2
GND
NOTES
1. R3, R4, AND R5 SELECTED FOR MATCHING AND TRACKING.
2. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
3. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIERS.
Figure 12. Bipolar Operation (4-Quadrant Multiplication)
VOUT
Rev. C | Page 8 of 12
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