UPD753108GK-XXX-9ET データシートの表示（PDF） - NEC => Renesas Technology
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UPD753108GK-XXX-9ET Datasheet PDF : 90 Pages
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µPD753104, 753106, 753108
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
P30
P31
P32
P33
P50-P53 Note 2
Input/Output
Input
Input/Output
Input/Output
Input/Output
Input
Input/Output
Input/Output
Input/Output
Alternate
Function
INT4
SCK
SO/SB0
SI/SB1
INT0
INT1
TI1/TI2/INT2
TI0
PTO0
PTO1
PCL/PTO2
BUZ
LCDCL
SYNC
–
–
–
Function
8-bit
I/O Circuit
After Reset
I/O
TYPE Note 1
4-bit input port (PORT0).
No
For P01 to P03, connection of on-chip pull-
up resistors can be specified by software in
3-bit units.
Input
(B)
(F)-A
(F)-B
(M)-C
4-bit input port (PORT1).
No
Connection of on-chip pull-up resistors can
be specified by software in 4-bit units.
P10/INT0 can select noise elimination
circuit.
Input
(B)-C
4-bit input/output port (PORT2).
No
Input
E-B
Connection of on-chip pull-up resistors can
be specified by software in 4-bit units.
Programmable 4-bit input/output port
No
(PORT3).
This port can be specified for input/output
bit-wise.
Connection of on-chip pull-up resistors can
be specified by software in 4-bit units.
Input
N-ch open-drain 4-bit input/output port
No High level
(PORT5).
A pull-up resistor can be contained bit-wise
(when pull-
up resistors
are provided)
(mask option).
or high-
Withstand voltage is 13 V in open-drain mode.
impedance
E-B
M-D
Notes 1.
2.
Characters in parentheses indicate the Schmitt trigger input.
If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port),
low-level input leakage current increases when input or bit manipulation instruction is executed.
9
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