HIP5061DS データシートの表示（PDF） - Intersil
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HIP5061DS Datasheet PDF : 20 Pages
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Specifications HIP5061
Electrical Specifications VDD = VG =12V, VC = 5V, VFB = 5.1V, SOURCE = GND = DRAIN = 0V, TJ = 0oC to +105oC,
Unless Otherwise Specified (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
CURRENT CONTROLLED PWM
gm(VC)
V/IREF
∆IDRAIN, PEAK /∆VC
Voltage to Current Converter Ref-
erence Voltage
Note 3
IDRAIN = 0.25A, Note 3
tBT
Current Comparator Blanking
Note 3
Time
tONMIN
tOFFMIN
MinCI
Minimum DMOS “ON” Time
Minimum DMOS “OFF” Time
Minimum Controllable DMOS
Peak Current
Note 3
Note 3
Note 3
MaxCI
Maximum Controllable DMOS
Peak Current
Duty Cycle = 6% to 30%, Note 3
MaxCI
Maximum Controllable DMOS
Peak Current
Duty Cycle = 30% to 96%, Note 3
CURRENT COMPENSATION RAMP
∆I/∆t
tRD
Compensation Ramp Rate
Compensation Ramp Delay
∆IDRAIN, PEAK /∆Time, Note 3
Note 3
START-UP
VDDMIN
VDDHYS
VCEN
Rising VDD Threshold Voltage
Power-On Hysteresis
Enable Comparator Threshold
Voltage
VFB = 4V
VFB = 4V
RVC
Power-Up Resistance
THERMAL MONITOR
4V < VDD < 10.8V, VC = 0.8V
TJ
Substrate Temperature for
Thermal Monitor to Trip
Note 4
TJHY
Temperature Hysteresis
Note 4
NOTES:
1. All Voltages relative to pin 1, GND.
2. VD = 10V, Starting TJ = +25oC, L = 4mH, IPEAK = 7A.
3. Test is performed at wafer level only.
4. Determined by design, not a measured parameter.
MIN
TYP
MAX
UNITS
1.4
2.2
3.0
A/V
2.4
2.8
3.1
V
40
100
175
ns
60
150
250
ns
40
125
200
ns
-
100
250
mA
7
9.5
12
A
5
8
12
A
-1.4
- 0.85
- 0.45
A/µs
1.3
1.5
1.8
µs
9.3
10.3
10.8
V
0.3
0.45
0.6
V
1.0
1.5
2.0
V
50
500
3000
Ω
105
-
145
oC
-
5
-
oC
TABLE 1. CONDITIONS FOR UNCLAMPED ENERGY CIRCUIT
VD (V)
10
IL
(PEAK AMPS)
5
L (mH)
40
EAS (mJ)
550
10
7
4TZ
120
6
10
0.33
18
6
12.5
0.14
12
NOTE: Device Selected to Obtain Peak Current without Clocking
7
HIP5061
1
VARY tP TO OBTAIN
REQUIRED PEAK IL
12V
tP
L
+
IL
-VD
FIGURE 1. UNCLAMPED ENERGY TEST CIRCUIT
7-55
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