HIP5061DS データシートの表示（PDF） - Intersil

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HIP5061DS

7A, High Efficiency Current Mode Controlled PWM Regulator

Intersil 

HIP5061

Pin Description

TERMINAL

NUMBER

DESIGNATION

DESCRIPTION

1

GND

This is the analog ground terminal of the IC.

2

VC

The output of the transconductance amplifier appears at this terminal. Input to the internal

voltage to current converter also appears at this node. Transconductance amplifier gain

and loop response are set at this terminal. When the VDD terminal voltage is below the

starting voltage, VDDMIN, this terminal is held low. When the voltage at this terminal

exceeds VCMAX, 7V typical, implying an over-current condition, a typical 10mA current,

IVCOVER pulls this terminal towards ground. This current remains “ON” until the voltage on

the VC terminal falls by VCHYS, typically 1.1V, below the upper threshold, VCMAX. When the

voltage on this terminal falls below VCEN, typically 1.5V, the IC is disabled.

3

FB

Feedback from the regulator output is applied to this terminal. This terminal is the input to

the transconductance amplifier. The amplifier compares the internal 5.1V reference and

the feedback signal from the regulator output.

4

SOURCE

The terminal, labeled TAB, has a connection to this terminal, but because of the long lead

length and resulting high inductance of this terminal, it should not be used as a means of

bypassing. Therefore, this terminal is labeled “Do Not Use.”

5

DRAIN

Connection to the Drain of the internal power DMOS transistor is made at this terminal.

6

VG

Gate drive supply voltage is provided at this terminal. A 10Ω to 150Ω resistor connected

between this terminal and the VDD terminal provides decoupling and the supply voltage

for the gate drivers.

7

VDD

External supply input to the IC. A nominal 14V shunt regulator is connected between this

terminal and the TAB. A series resistor should be connected to this terminal from the

external voltage source to supply a minimum current of 33mA and a maximum current of

105mA under the worst cast supply voltage. The series resistor is not required if the

supply voltage is 12V, ±10%.

TAB

SOURCE

This is the internal power DMOS transistor Source terminal. It should be used as the

ground return for the VDD bypass capacitor. In addition high frequency bypassing for both

the regulator output load voltage and supply input voltage should be returned to this

terminal.

For more information refer to Application Notes AN9208, AN9212, AN9323.

Foot Print For Soldering

0.120

0.523

OPTIONAL Ø 0.151

LIMIT OF SOLDER MASK

FOR HEADER

0.212

0.424

0.050 TYP

0.480

0.575

0.675

TO-220 STAGGERED GULL WING SIP

0.050 TYP

0.080 TYP

7-58

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