GS74116AGP-10I(2013) データシートの表示（PDF） - Giga Semiconductor

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GS74116AGP-10I
(Rev.:2013)

256K x 16 4Mb Asynchronous SRAM

Giga Semiconductor 

GS74116AGP/X

AC Characteristics

Read Cycle

Parameter

Read cycle time

Address access time

Chip enable access time (CE)

Byte enable access time (UB, LB)

Output enable to output valid (OE)

Output hold from address change

Chip enable to output in low Z (CE)

Output enable to output in low Z (OE)

Byte enable to output in low Z (UB, LB)

Chip disable to output in High Z (CE)

Output disable to output in High Z (OE)

Byte disable to output in High Z (UB, LB)

-8

-10

-12

Symbol

Unit

Min Max Min Max Min Max

tRC

8

—

10

—

12

—

ns

tAA

—

8

—

10

—

12

ns

tAC

—

8

—

10

—

12

ns

tAB

—

3.5

—

4

—

5

ns

tOE

—

3.5

—

4

—

5

ns

tOH

3

—

3

—

3

—

ns

tLZ*

3

—

3

—

3

—

ns

tOLZ*

0

—

0

—

0

—

ns

tBLZ*

0

—

0

—

0

—

ns

tHZ*

—

4

—

5

—

6

ns

tOHZ*

—

3.5

—

4

—

5

ns

tBHZ*

—

3.5

—

4

—

5

ns

* These parameters are sampled and are not 100% tested.

Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL

Address

Data Out

tOH

Previous Data

tRC

tAA

Data valid

Rev: 1.10 1/2013

6/13

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2001, GSI Technology

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