T431616A-7C データシートの表示（PDF） - Taiwan Memory Technology
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T431616A-7C Datasheet PDF : 31 Pages
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tm TE
CH
T431616A
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1 CKEn CS RAS CAS WE DQM BA A10/AP A9~A0 Note
Register Mode Register Set H
X L L LL X
X
1,2
Auto Refresh
H
H
L L LH X
X
3
Refresh Self
Entry
L
Refresh Exit
L
H L H HH X
X
3
H X XX
Bank Active & Row Address
H
X L L H H X V Row Address
Read Column Auto Precharge Disable
Address
Auto Precharge Enable
H
Write & Column Auto Precharge Disable
Address
Auto Precharge Enable
H
Burst Stop
H
L
Column
X L H LH XV
Address 4,5
H
(A0~A7)
L
Column
X L H L L XV
Address 4,5
H
(A0~A7)
X L H HL X
X
6
Bank Selection
VL
Precharge
Both Banks
H
X L L HL XX H
4
Clock Suspend or
Active Power Down
Entry
H
L H X XX X
L V VV
Exit
L
H X X XX X
X
Precharge Power Down
Entry
H
L
H
L
X
H
XX
HH
X
Mode
Exit
L
H
H
L
X
V
XX
VV
X
X
DQM
H
X
V
X
7
No Operation Command
H
H
X
H
L
X
H
XX
HH
X
X
(V=Valid , X=Don’t Care , H=Logic High , L=logic Low)
Notes :
1. OP Code : Operation Code. A0~A10/AP , BA : Program keys.(@MRS)
2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row
precharge command is meant by ‘Auto’. Auto / self refresh can be issued only at both banks precharge state.
4. BA : Bank select address.
If ’Low’ : at read , wriye , row active and precharge , bank A is selected.
If ‘High’ : at read , wriye , row active and precharge , bank B is selected.
If A10/AP is ‘High’ : at row precharge , BA ignored and both banks are selected.
5. During burst read or write with auto precharge , new read/write command cannotbeissued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Taiwan Memory Technology, Inc. reserves the right P.13
to change products or specifications without notice.
Publication Date: DEC. 2000
Revision: C
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