P89LPC9351(2008) データシートの表示（PDF） - NXP Semiconductors.

部品番号

コンポーネント説明

メーカー

P89LPC9351
(Rev.:2008)

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 8-bit ADC

NXP Semiconductors. 

NXP Semiconductors

P89LPC9351

8-bit microcontroller with 8-bit ADC

Table 3. Pin description …continued

Symbol

Pin

Type Description

PLCC28,

TSSOP28

P2.0 to P2.7

I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset

Port 2 latches are configured in the input only mode with the internal pull-up

disabled. The operation of Port 2 pins as inputs and outputs depends upon the

port configuration selected. Each port pin is configured independently. Refer to

Section 7.16.1 “Port configurations” and Table 10 “Static characteristics” for

details.

All pins have Schmitt trigger inputs.

Port 2 also provides various special functions as described below:

P2.0/ICB/DAC0 1

/AD03

I/O P2.0 — Port 2 bit 0.

I

ICB — Input Capture B.

O DAC0 — Digital-to-analog converter output.

I

AD03 — ADC0 channel 3 analog input.

P2.1/OCD/AD02 2

I/O P2.1 — Port 2 bit 1.

O OCD — Output Compare D.

I

AD02 — ADC0 channel 2 analog input.

P2.2/MOSI

13

I/O P2.2 — Port 2 bit 2.

I/O MOSI — SPI master out slave in. When configured as master, this pin is output;

when configured as slave, this pin is input.

P2.3/MISO

14

I/O P2.3 — Port 2 bit 3.

I/O MISO — When configured as master, this pin is input, when configured as slave,

this pin is output.

P2.4/SS

15

I/O P2.4 — Port 2 bit 4.

I/O SS — SPI Slave select.

P2.5/SPICLK

16

I/O P2.5 — Port 2 bit 5.

I/O SPICLK — SPI clock. When configured as master, this pin is output; when

configured as slave, this pin is input.

P2.6/OCA

27

I/O P2.6 — Port 2 bit 6.

O OCA — Output Compare A.

P2.7/ICA

28

I/O P2.7 — Port 2 bit 7.

I

ICA — Input Capture A.

P3.0 to P3.1

I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset

Port 3 latches are configured in the input only mode with the internal pull-up

disabled. The operation of Port 3 pins as inputs and outputs depends upon the

port configuration selected. Each port pin is configured independently. Refer to

Section 7.16.1 “Port configurations” and Table 10 “Static characteristics” for

details.

All pins have Schmitt trigger inputs.

Port 3 also provides various special functions as described below:

P89LPC9351_1

Preliminary data sheet

Rev. 01 — 19 November 2008

© NXP B.V. 2008. All rights reserved.

9 of 74

Share Link: