M35080 データシートの表示（PDF） - STMicroelectronics

部品番号

コンポーネント説明

メーカー

M35080

8 Kbit Serial SPI Bus EEPROM With Incremental Registers

STMicroelectronics 

Figure 10. Write Data to Incremental Registers (WRINC)

M35080

S

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

C

INSTRUCTION

16 BIT ADDRESS

DATA BYTE 1

D

15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

S

32 33 34 35 36 37 38 39

C

DATA BYTE 2

D

76543210

Note: 1. The most significant address bits, A15-A10, are treated as Don’t Care.

AI02146B

WIP bits. WIP is high during the self-timed write

cycle. When the cycle is completed, the write en-

able latch is reset.

Page Write Operation

A maximum of 32 bytes of data can be written dur-

ing one Write time, tW, provided that they are all to

the same page (see Figure 11). The Page Write

operation is the same as the Byte Write operation,

except that instead of deselecting the device after

the first byte of data, up to 31 additional bytes can

be shifted in (and the device is deselected after the

last byte).

Any address of the memory can be chosen as the

first address to be written. If the address counter

reaches the end of the page (an address of the

form xxxx xxxx xxx1 1111) and the clock contin-

ues, the counter rolls over to the first address of

the same page (xxxx xxxx xxx0 0000) and over-

writes any previously written data.

As before, the Write cycle only starts if the S tran-

sition occurs just after the eighth bit of the last data

byte has been received, as shown in Figure 12.

DATA PROTECTION AND PROTOCOL SAFETY

To protect the data in the memory from inadvertent

corruption, the memory device only responds to

correctly formulated commands. The main securi-

ty measures can be summarized as follows:

– The WEL bit is reset at power-up.

– S must rise after the eighth clock count (or mul-

tiple thereof) in order to start a non-volatile write

cycle (in the memory array or in the status reg-

ister).

– Accesses to the memory array are ignored dur-

ing the non-volatile programming cycle, and the

programming cycle continues unaffected.

– After execution of a WREN, WRDI, or RDSR in-

struction, the device enters a wait state, and

waits to be deselected.

– Invalid S transitions are ignored.

9/18

Share Link: