M29DCL1-8T データシートの表示（PDF） - STMicroelectronics
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M29DCL1-8T
STMicroelectronics
M29DCL1-8T Datasheet PDF : 40 Pages
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M29W800AT, M29W800AB
Command Interface
Instructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and
fifth cycles are used to input Coded cycles to the
C.I. This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The 'Com-
mand' itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset the device to Read Array mode.
Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signa-
ture or Block Protection Status), Program, Block
Erase, Chip Erase, Erase Suspend and Erase Re-
sume.
The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase op-
erations. The Status Register Data Polling,
Toggle, Error bits and the RB output may be read
at any time, during programming or erase, to mon-
itor the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all in-
structions (see Table 8).
The third cycle inputs the instruction set-up com-
mand. Subsequent cycles output the addressed
data, Electronic Signature or Block Protection Sta-
tus for Read operations. In order to give additional
data protection, the instructions for Program and
Block or Chip Erase require further command in-
puts. For a Program instruction, the fourth com-
mand cycle inputs the address and data to be
programmed. For an Erase instruction (Block or
Chip), the fourth and fifth cycles input a further
Coded sequence before the Erase confirm com-
mand on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data
from another block or to program data in another
block, and then resumed. When power is first ap-
plied or if VCC falls below VLKO, the command in-
terface is reset to Read Array.
Figure 3. TSOP Connections
A15 1
48 A16
A14
BYTE
A13
VSS
A12
DQ15A–1
A11
DQ7
A10
DQ14
A9
DQ6
A8
DQ13
NC
DQ5
NC
DQ12
W
DQ4
RP 12 M29W800T 37 VCC
NC 13 M29W800B 36 DQ11
NC
DQ3
RB
DQ10
A18
DQ2
A17
DQ9
A7
DQ1
A6
DQ8
A5
DQ0
A4
G
A3
VSS
A2
E
A1 24
25 A0
AI02179
Figure 4. SO Connections
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11 M29W800T 34
12 M29W800B 33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
AI02181
RP
W
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
6/40
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