MAX456 データシートの表示（PDF） - Maxim Integrated
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MAX456 Datasheet PDF : 12 Pages
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8 x 8 Video Crosspoint Switch
______________________________________________________________Pin Description
PIN
DIP
PLCC
NAME
FUNCTION
—
1, 12, 23, 34
N.C.
No connect. Not internally connected.
1
2
D1/SER OUT
Parallel Data Bit D1
multiple parts when
wSEheRn/P—SA—ER–R=/P—5A—VR–.
=
0V.
Serial
Output
for
cascading
2
3
D0/SER IN
PSaErRa/lPl—eA—l RD– a=ta5VB.it D0 when SER/P—A—R– = 0V. A Serial Input when
3, 4, 6
4, 5, 7
A2, A1, A0
Output Buffer Address Lines
5, 7, 9, 11,
13, 15, 17, 19
6, 8, 10, 13,
15, 17, 19, 21
IN0–IN7
Video lnput Lines
8
10, 12
9
11, 14
LOAD
DGND
Asynchronous control line. When LOAD = 1, all the 400Ω internal active
loads are on. When LOAD = 0, external 400Ω loads must be used. The
buffers MUST have a resistive load to maintain stability.
Digital Ground Pins. Both DGND pins must have the same potential and
be bypassed to AGND. DGND should be within ±0.3V of AGND.
When this control line is high, the 2nd-rank registers are loaded with the
14
16
EDGE/L–—E—V—E—L–
rising edge of the LATCH line. If this control line is low, the 2nd-rank reg-
isters are transparant when LATCH is low, passing data directly from the
1st-rank registers to the decoders.
16, 26, 40
18
18, 29, 44
20
V+
SER/P—A—R–
All V+ pins must be tied to each other and bypassed to AGND
separately (Figure 2).
5V = 32-Bit Serial, 0V = 7-Bit Parallel
20, 34
21
22
23
24
22, 38
24
25
26
27
V-
WR
LATCH
C—E–
CE
Both V- pins must be tied to each other and bypassed to AGND
separately (Figure 2).
WRITE in the serial mode, shifts data in. In the parallel mode, WR loads
data into the 1st-rank registers. Data is latched on the rising edge.
If EDGE/–L—E—V—E—L– = 5V, data
rank registers on the rising
is loaded from the
edge of LATCH. If
1EsDt-GraEn/L–—kE—reV—gE—iL–st=ers0Vto,
the 2nd-
data is
loaded while LATCH = 0V. In addition, data is loaded during the execution
of parallel-mode functions 1011 through 1110, or if LATCH = 5V during the
execution of the parallel-mode "software-LATCH" command (1111).
–C—h——ip——E—n—a—b——le–. When –C—E– = 0V and CE = 5V, the WR line is enabled.
Chip Enable. When –C—E– = 0V and CE = 5V, the WR line is enabled.
25, 27, 29, 31, 28, 30, 32, 35,
33, 35, 37, 39 37, 39, 41, 43
OUT7-OUT0
Output Buffers 7-0 (Note 1)
28, 30, 32
36
38
31, 33, 36
40
42
AGND
D3
D2
Analog Ground must be at 0.0V since the gain resistors of the buffers are
tied to these 3 pins.
Parallel Data Bit D3 when SER/ –P—A—R– = 0V. When D3 = 0V, D0-D2 specifies
the input channel to be connected to buffer. When D3 = 5V, then D0-D2
specify control codes. D3 is not used when SER/–P—A—R– = 5V.
Parallel Data Bit D2 when SER/ P–—A—R– = 0V. Not used when
SER/ –P—A—R– = 5V.
Note 1: Buffer inputs are internally grounded with a 1000 or 1001 command from the D3-D0 lines. AGND must be at 0.0V since the
gain setting resistors of the buffers are internally tied to AGND.
4 _______________________________________________________________________________________
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