CXD2302Q データシートの表示（PDF） - Sony Semiconductor

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CXD2302Q

8-bit 50MSPS Video A/D Converter with Clamp Function

Sony Semiconductor 

Timing Chart II

Analog input

CXD2302Q

Vi (1)

Vi (2)

Vi (3)

Vi (4)

External clock

Upper comparators block

Upper data

(1)

(2)

(3)

(4)

S (1)

C (1) S (2) C (2) S (3) C (3)

S (4)

C (4)

MD (0)

MD (1)

MD (2)

MD (3)

Lower reference voltage

RV (0)

RV (1)

RV (2)

RV (3)

Lower comparators A block

Lower data A

S (1)

H (1)

LD (–1)

C (1) S (3)

H (3)

LD (1)

C (3)

Lower comparators B block

Lower data B

H (0)

C (0) S (2)

LD (–2)

H (2)

LD (0)

C (2) S (4)

H (4)

LD (2)

Digital output

Out (–2)

Out (–1)

Out (0)

Out (1)

Operation (See Block Diagram and Timing Chart II)

1. The CXD2302Q is a 2-step parallel system A/D converter featuring a 4-bit upper comparator block and 2

lower comparator blocks of 4-bit each. The reference voltage that is equal to the voltage between VRT –

VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper

data is fed through the reference supply to the lower 4-bit comparator block. VRTS and VRBS pins serve

for the self generation of VRT (Reference voltage top) and VRB (Reference voltage bottom), and they are

also used as the sence pins as shown in the Application Circuit examples I-4 and I-5.

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