HD74HC259 データシートの表示（PDF） - Hitachi -> Renesas Electronics

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HD74HC259

8-bit Addressable Latch

Hitachi -> Renesas Electronics 

HD74HC259

8-bit Addressable Latch

Description

The HD74HC259 has a single data input (D), 8 latch outputs (Q0-Q7), 3 address inputs (A, B, and C), a

common enable input (E), and a common clear input. To operate this device as an addressable latch, data is

held on the D input, and the address of the latch into which the data is to be entered is held on the A, B and

C inputs. When enable is taken low the data flows through to the addressed output. The data is stored

when enable transitions from low to high. All unaddressed latches will remain unaffected. With enable in

the high state the device is deselected, and all latches remain in their previous state, unaffected by changes

on the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the

enable should be held high (inactive) while the address lines are changing.

If enable is held high and clear is taken low all eight latches are cleared to a low state. If enable is low all

latches except the addressed latch will be cleared. The addressed latch will instead follow the D input,

effectively implementing a 3-to-8 line decoder.

Features

• High Speed Operation: tpd (Data to Output) = 16 ns typ (CL = 50 pF)

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: VCC = 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

Function Table

Inputs

Clear G

H

L

H

H

L

L

L

H

Output of Addressed Latch Each Other Output

D

Qio

Qio

Qio

D

L

L

L

Function

Addressable latch

Memory

8-line demultiplexer

Clear

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