PCA9500 データシートの表示（PDF） - Philips Electronics

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PCA9500

8-bit I2C and SMBus I/O port with 2-kbit EEPROM

Philips Electronics 

Philips Semiconductors

8-bit I2C and SMBus I/O port with 2-kbit EEPROM

Product data sheet

PCA9500

FUNCTIONAL DESCRIPTION

WRITE PULSE

DATA FROM

SHIFT REGISTER

POWER-ON

RESET

READ PULSE

DATA TO

SHIFT REGISTER

DQ

FF

CI

S

DQ

FF

CI

S

100 µA

Figure 4. Simplified schematic diagram of each I/O

VDD

I/O0 TO I/O7

VSS

SW00546

DEVICE ADDRESSING

Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9500 is shown in

Figure 5. Internal pullup resistors are incorporated on the hardware selectable address pins.

SLAVE ADDRESS

SLAVE ADDRESS

0 1 0 0 A2 A1 A0 R/W

1 0 1 0 A2 A1 A0 R/W

(a) I/O EXPANDER

(b) MEMORY

FIXED

HARDWARE

PROGRAMMABLE

a.

FIXED

HARDWARE

PROGRAMMABLE

b.

SW01075

Figure 5. PCA9500 slave addresses

The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write

operation.

2004 Sep 30

4

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