PC85132/232-1 データシートの表示（PDF） - NXP Semiconductors.

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PC85132/232-1

LCD driver for low multiplex rates

NXP Semiconductors. 

NXP Semiconductors

PCA85132

LCD driver for low multiplex rates

exchanged (see Section 7.5.4 on page 25) with alternate RAM banks at the blink

frequency. This mode can also be specified by the blink-select command (see Table 11 on

page 8).

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD elements can blink selectively by changing the display RAM data at fixed time

intervals.

The entire display can blink at a frequency other than the nominal blinking frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 6).

7.2 Power-On Reset (POR)

At power-on, the PCA85132 resets to the following starting conditions:

• All backplane and segment outputs are set to VLCD

• The selected drive mode is 1:4 multiplex with 1⁄3 bias

• Blinking is switched off

• Input and output bank selectors are reset

• The I2C-bus interface is initialized

• The data pointer and the subaddress counter are cleared (set to logic 0)

• The display is disabled (bit E = 0, see Table 6 on page 6)

• If internal oscillator is selected (pin OSC connected to VSS), then there is no clock

signal on pin CLK

Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.3 Possible display configurations

The display configurations possible with the PCA85132 depend on the required number of

active backplane outputs. A selection of display configurations is given in Table 14.

All of the display configurations given in Table 14 can be implemented in a typical system

as shown in Figure 5.

PCA85132

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 9 April 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

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