PC85132/232-1 データシートの表示（PDF） - NXP Semiconductors.

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PC85132/232-1

LCD driver for low multiplex rates

NXP Semiconductors. 

NXP Semiconductors

PCA85132

LCD driver for low multiplex rates

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Fig 3. Frequency generation of the PCA85132

Remark: A clock signal must always be supplied to the device. Removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.1.6.2 Internal clock

If the internal oscillator is used, the timing of the PCA85132 is derived from the built-in

oscillator by a pre-scaler which can be configured with the frequency-ctrl command (see

Table 12).

The internal oscillator is calibrated within an accuracy of ±3.9 % (at VDD = 5.0 V;

Tamb = 30 °C).

The frequency-ctrl command determines the division factor between the oscillator

frequency fosc and the internal clock frequency fclk(int). If the internal oscillator is used, the

frame frequency is derived from the internal clock frequency fclk(int) by the fixed division

shown in Equation 1 on page 9.

If the display is enabled (see bit E in Table 6), fclk(int) on pin CLK provides the clock signal

for cascaded LCD drivers in the system. For further information about cascading, see

Section 14.4 on page 44. The value range of fosc is specified in Table 22 on page 38.

7.1.6.3 External clock

If the external clock source is selected, the timing frequency of the PCA85132 is the

external clock frequency. In this case, the frequency-ctrl command has no influence on

the clock frequency nor the frame frequency. The frame frequency is derived from the

external clock frequency fclk(ext) by the fixed division as shown in Equation 1.

7.1.6.4 Frame frequency

Sourced by the internal oscillator or an external clock, the frame frequency is derived from

the clock frequency fclk by Equation 1.

ffr

=

-f-c---l--k

24

(1)

PCA85132

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 9 April 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

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