PCA9541PW データシートの表示（PDF） - NXP Semiconductors.

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PCA9541PW

2-to-1 I2C-bus master selector with interrupt logic and reset

NXP Semiconductors. 

NXP Semiconductors

PCA9541

2-to-1 I2C-bus master selector with interrupt logic and reset

8. Functional description

Refer to Figure 1 “Block diagram of PCA9541”.

8.1 Device address

Following a START condition, the upstream master that wants to control the I2C-bus or

make a status check must send the address of the slave it is accessing. The slave

address of the PCA9541 is shown in Figure 5. To conserve power, no internal pull-up

resistors are incorporated on the hardware selectable pins and they must be pulled HIGH

or LOW.

1 1 1 A3 A2 A1 A0 R/W

fixed

hardware

selectable

002aab390

Fig 5. Slave address

The last bit of the slave address defines the operation to be performed. When set to

logic 1 a read is selected, while logic 0 selects a write operation.

Remark: Reserved I2C-bus addresses must be used with caution since they can interfere

with:

• ‘reserved for future use’ I2C-bus addresses (1111 1XX)

• slave devices that use the 10-bit addressing scheme (1111 0XX)

8.2 Command Code

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9541, which will be stored in the Command Code register.

0 0 0 AI 0 0 B1 B0

auto-increment

register number

002aab391

Fig 6. Command Code

The 2 LSBs are used as a pointer to determine which register will be accessed.

If the auto-increment flag is set (AI = 1), the two least significant bits of the Command

Code are automatically incremented after a byte has been read or written. This allows the

user to program the registers sequentially or to read them sequentially.

• During a read operation, the contents of these bits will roll over to 00b after the last

allowed register is accessed (10b).

PCA9541_7

Product data sheet

Rev. 07 — 2 July 2009

© NXP B.V. 2009. All rights reserved.

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