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PCA9539A データシートの表示(PDF) - NXP Semiconductors.

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PCA9539A Datasheet PDF : 39 Pages
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NXP Semiconductors
PCA9539A
Low voltage 16-bit I2C-bus I/O port with interrupt and reset
6.2 Registers
6.2.1 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCA9539A. The lower
four bits of this data byte state the operation (read or write) and the internal registers
(Input, Output, Polarity Inversion, or Configuration) that will be affected. This register is
write only.
B7 B6 B5 B4 B3 B2 B1 B0
002aaf540
Fig 5. Pointer register bits
Table 4. Command byte
Pointer register bits
Command byte Register
B7 B6 B5 B4 B3 B2 B1 B0 (hexadecimal)
00000000
00h
Input port 0
00000001
01h
Input port 1
00000010
02h
Output port 0
00000011
03h
Output port 1
00000100
04h
Polarity Inversion port 0
00000101
05h
Polarity Inversion port 1
00000110
06h
Configuration port 0
00000111
07h
Configuration port 1
Protocol
Power-up
default
read byte
read byte
read/write byte
read/write byte
read/write byte
read/write byte
read/write byte
read/write byte
xxxx xxxx[1]
xxxx xxxx
1111 1111
1111 1111
0000 0000
0000 0000
1111 1111
1111 1111
[1] Undefined.
6.2.2 Input port register pair (00h, 01h)
The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by the Configuration
register. The Input port registers are read only; writes to these registers have no effect.
The default value ‘X’ is determined by the externally applied logic level. An Input port
register read operation is performed as described in Section 7.2 “Reading the port
registers”.
Table 5. Input port 0 register (address 00h)
Bit
7
6
5
4
3
2
1
0
Symbol I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
Default
X
X
X
X
X
X
X
X
Table 6. Input port 1 register (address 01h)
Bit
7
6
5
4
3
2
1
0
Symbol I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
Default
X
X
X
X
X
X
X
X
PCA9539A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 26 September 2012
© NXP B.V. 2012. All rights reserved.
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