PCD5002A データシートの表示（PDF） - Philips Electronics

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PCD5002A

Enhanced Pager Decoder for APOC1/POCSAG

Philips Electronics 

Philips Semiconductors

Enhanced Pager Decoder for

APOC1/POCSAG

Product specification

PCD5002A

7 PINNING

SYMBOL PIN

DESCRIPTION

ATL

1 alert LOW level output

ALC

2 alert control input (normally LOW by

internal pull-down)

DON

3 direct ON/OFF input (normally LOW by

internal pull-down)

REF

4 real-time clock frequency reference

output

INT

5 interrupt output

n.c.

6 not connected

RST

7 reset input (normally LOW by internal

pull-down)

VPR

SDA

SCL

8 external positive voltage reference

input

9 I2C-bus serial data input/output

10 I2C-bus serial clock input

VDD

VSS

VPO

CCP

11 main positive supply voltage

12 main negative supply voltage

13 voltage converter positive output

14 voltage converter shunt capacitor

(positive side)

CCN

15 voltage converter shunt capacitor

(negative side)

SYMBOL PIN

DESCRIPTION

TS1

16 test input 1 (normally LOW by internal

pull-down)

XTAL2 17 decoder crystal oscillator output

XTAL1 18 decoder crystal oscillator input

n.c.

19 not connected

TS2

20 test input 2 (normally LOW by internal

pull-down)

BAT

21 battery sense input

DQC

22 demodulator quick charge output

RDI

23 received data input (POCSAG or

APOC1)

RXE

24 receiver circuit enable output

ROE

25 receiver oscillator enable output

ZSD

26 synthesizer serial data output

ZSC

27 synthesizer serial clock output

ZLE

28 synthesizer latch enable output

VSS

29 main negative supply voltage

VIB

30 vibrator motor drive output

LED

31 LED drive output

ATH

32 alert HIGH level output

handbook, full pagewidth

1999 Jan 08

ATL 1

ALC 2

DON 3

REF 4

INT 5

n.c. 6

RST 7

VPR 8

PCD5002AH

24 RXE

23 RDI

22 DQC

21 BAT

20 TS2

19 n.c.

18 XTAL1

17 XTAL2

MGL564

Fig.2 Pin configuration.

5

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