PCD5002AH データシートの表示（PDF） - Philips Electronics
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PCD5002AH Datasheet PDF : 48 Pages
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Philips Semiconductors
Enhanced Pager Decoder for
APOC1/POCSAG
Product specification
PCD5002A
Address code-words are identified by an MSB at logic 0
and are coded as shown in Fig.3. A user address or RIC
consists of 21 bits. Only the upper 18 bits are encoded in
the address code-word (bits 2 to 19). The lower 3 bits
designate the frame number (0 to 7) in which the address
is transmitted.
Four different call types (‘numeric’, ‘alphanumeric’ and two
‘alert only’ types) can be distinguished. The call type is
determined by two function bits in the address code-word
(bits 20 and 21), as shown in Table 1.
Alert-only calls consist only of a single address code-word.
Numeric and alphanumeric calls have message
code-words following the address. A message causes the
frame structure to be temporarily suspended. Message
code-words are sent until the message is completed, with
only the sync words being transmitted in their expected
positions.
Message code-words are identified by an MSB at logic 1
and are coded as shown in Fig.3. The message
information is stored in a 20-bit field (bits 2 to 21).
The standard data format is determined by the call type:
4 bits per digit for numeric messages and 7 bits per
(ASCII) character for alphanumeric messages.
Each code-word is protected against transmission errors
by 10 CRC check bits (bits 22 to 31) and an even-parity bit
(bit 32).
This permits correction of a maximum of 2 random errors
or up to 3 errors in a burst of 4 bits (a 4-bit burst error) per
code-word.
8.3 The APOC1 paging code
The APOC1 paging code is fully POCSAG compatible and
involves the introduction of batch grouping and a Batch
Zero Identifier (BZI). This reserved address code-word
indicates the start of a ‘cycle’ of 5 or 15 batches long and
is transmitted immediately after a sync word.
Cycle transmission must be coherent i.e. a transmission
starting an integer number of cycle periods after the start
of the previous one.
Broadcast message data may be included in a
transmission. This information may occupy any number of
message code-words and immediately follows the batch
zero identifier of the first cycle after preamble.
The presence of data is indicated by the function bits in the
batch zero identifier: 1,1 indicates ‘no broadcast data’.
Any other combination indicates a broadcast message.
The PCD5002A can be configured for POCSAG or
APOC1 operation via SPF programming. The batch zero
identifier is programmable and can be stored in any
identifier location in EEPROM.
The POCSAG standard only allows combinations of data
formats and function code bits as given in Table 1.
However, other (non-standard) combinations will be
decoded normally by the PCD5002A.
handbook, full pagewidth
PREAMBLE BATCH 1
BATCH 2
BATCH 3
LAST BATCH
10101 . . . 10101010
SYNC | CW CW | CW CW | . . . . . | CW CW
FRAME 0 FRAME 1
FRAME 7
1999 Jan 08
Address code-word 0 18-bit address 2 function bits 10 CRC bits P
Message code-word 1 20-bit message
Fig.3 POCSAG code structure.
10 CRC bits P
MCD456
7
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