PCD5003AH データシートの表示（PDF） - Philips Electronics
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PCD5003AH Datasheet PDF : 44 Pages
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Philips Semiconductors
Enhanced Pager Decoder for POCSAG
Product specification
PCD5003A
7.21 Demodulator quick charge
Two modes of operation are available that determine the
periods when the DQC is set.
The operating mode is selected by EEPROM
programming of SPF byte 3, bit D5:
• Mode 0 (D5 = 0): DQC is active (logic HIGH) during the
receiver establishment time tRXE in all ACCESS modes
except data receive and data fail. During switch-on,
DQC is active for 1 code-word duration.
• Mode 1 (D5 = 1): DQC is active during sync word
detection in all ACCESS modes. During switch-on and
preamble receive modes, DQC is active continuously.
The timing of DQC is as follows: (see Fig.5).
• Mode 0: Set along with RXE output (time tRXE before the
first code-word is expected); cleared during the second
bit of the code-word following tRXE.
• Mode 1: Set during the second bit of the sync word;
cleared after the last bit of the sync word.
Note: During switch-on, tRXE is not used: RXE and DQC
are switched on immediately.
handbook, full pagewidthData into RDI
RXE
Mode 0 DQC
Mode 1 DQC
code-word
code-word
tRXE
code-word
MGL566
Fig.5 Example of DQC timing.
7.22 Battery condition input
A logic signal from an external sense circuit signalling
battery condition can be applied to the BAT input. This
input is sampled each time the receiver is disabled
(RXE ↓ 0).
When enabled via the control register (D2 = 0), the
condition of input BAT is reflected in bit D6 of the status
register. Each change of state of bit D6 causes an external
interrupt at output INT.
When using the UAA2080 pager receiver a battery-low
condition corresponds to a logic HIGH-level. With a
different sense circuit the reverse polarity can be used as
well, because every change of state is signalled to an
external controller.
After a reset the initial condition of the battery-low indicator
in the status register is zero.
1999 Jan 08
14
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