PCD5003AH データシートの表示（PDF） - Philips Electronics
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PCD5003AH Datasheet PDF : 44 Pages
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Philips Semiconductors
Enhanced Pager Decoder for POCSAG
Product specification
PCD5003A
handbook, full pagewidth
FROM
MASTER
FROM
SLAVE
S = START condition
P = STOP condition
A = Acknowledge
N = Not acknowledge
(a)
S
SLAVE ADDRESS
R/W A INDEX A
DATA
A
DATA
AP
0 (write)
index
address
n bytes with acknowledge
(b)
S
SLAVE ADDRESS
R/W A
DATA
A
DATA
NP
1 (read)
n bytes with acknowledge
(c) S SL. ADR. R/W A INDEX A DATA A S SL. ADR. R/W A DATA N P
0 (write)
index
address
(a) Master writes to slave.
(b) Master reads from slave.
(c) Combined format (shown: write plus read).
n bytes with
acknowledge
1 (read)
change of direction
n bytes with
acknowledge
MLC250
Fig.8 Message types.
7.25 Decoder I2C-bus access
All internal access to the PCD5003A takes place via the
I2C-bus interface. For this purpose the internal registers,
SRAM and EEPROM have been memory mapped and are
accessed via an index register. Table 13 shows the index
addresses of all internal blocks.
Registers are addressed directly, while RAM and
EEPROM are addressed indirectly via address pointers
and I/O registers.
Remark: The EEPROM memory map is non-contiguous
and organized as a matrix. The EEPROM address pointer
contains both row and column indicators.
Data written to read-only bits will be ignored. Values read
from write-only bits are undefined and must be ignored.
Each I2C-bus write message to the PCD5003A must start
with its slave address, followed by the index address of the
memory element to be accessed. An I2C-bus read
message uses the last written index address as a data
source. The different I2C-bus message types are shown in
Fig.8.
As a slave the PCD5003A cannot initiate bus transfers by
itself. To prevent an external controller from having to
monitor the operating status of the decoder, all important
events generate an external interrupt on output INT.
1999 Jan 08
17
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