PCD5003AH データシートの表示（PDF） - Philips Electronics

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PCD5003AH

Enhanced Pager Decoder for POCSAG

Philips Electronics 

Philips Semiconductors

Enhanced Pager Decoder for POCSAG

Product specification

PCD5003A

1 FEATURES

• Wide operating supply voltage range: 1.5 to 6.0 V

• EEPROM programming requires only 2.0 V supply

• Low operating current: 50 µA typ. (ON),

25 µA typ. (OFF)

• Temperature range: −25 to +70 °C

• “CCIR Radio paging Code No. 1” (POCSAG)

compatible

• 512, 1200 and 2400 bits/s data rates using 76.8 kHz

crystal

• Built-in data filter (16-times oversampling) and bit clock

recovery

• Advanced ACCESS® synchronization algorithm

• 2-bit random and (optional) 4-bit burst error correction

• Up to 6 user addresses Receiver Identity Codes (RICs),

each with 4 functions/alert cadences

• Up to 6 user address frames, independently

programmable

• Optional automatic call termination when bit error rate is

high

• Standard POCSAG sync word, plus up to 4 user

programmable sync words

• Received data inversion (optional)

• Call alert via beeper, vibrator or LED

• 2-level acoustic alert using single external transistor

• Alert control: automatic (POCSAG type), via cadence

register or alert input pin

• Separate power control of receiver and RF-oscillator for

battery economy

• Dedicated pin for easy control of superheterodyne

receiver

• Synthesizer set-up and control interface (3-line serial)

• On-chip EEPROM for storage of user addresses (RICs),

pager configuration and synthesizer data

• On-chip SRAM buffer for message data

• Slave I2C-bus interface to microcontroller for transfer of

message data, status/control and EEPROM

programming (data transfer at up to 400 kbits/s)

• Wake-up interrupt for microcontroller, programmable

polarity

• Direct and I2C-bus control of operating status (ON/OFF)

• Battery-low indication (external detector)

• Out-of-range condition indication

• Real-time clock reference output

• On-chip voltage doubler

• Interfaces directly to UAA2080 and UAA2082 paging

receivers.

2 APPLICATIONS

• Display pagers, basic alert-only pagers

• Information services

• Personal organizers

• Telepoint

• Telemetry/data transmission.

3 GENERAL DESCRIPTION

The PCD5003A is a very low power POCSAG decoder

and pager controller. It supports data rates of 512,

1200 and 2400 bits/s using a single 76.8 kHz crystal.

On-chip EEPROM is programmable using a minimum

supply voltage of 2.0 V, allowing ‘over-the-air’

programming. The PCD5003A is fast I2C-bus compatible

(maximum 400 kbits/s).

4 ORDERING INFORMATION

TYPE

NUMBER

PCD5003AH

NAME

LQFP32

PACKAGE

DESCRIPTION

plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm

VERSION

SOT358-1

1999 Jan 08

3

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