PCF8534 データシートの表示（PDF） - Philips Electronics

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PCF8534

Universal LCD driver for low multiplex rat

Philips Electronics 

NXP Semiconductors

PCF8534

Universal LCD driver for low multiplex rates

VDD

R tr

2CB

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

VSS

SDA

SCL

OSC

VDD VLCD

PCF8534

60 segment drives

4 backplanes

LCD PANEL

(up to 240

elements)

A0 A1 A2 SA0 VSS

MGL744v02

Fig 3. Typical system configuration

6.1 Power-on-reset

At power on the PCF8534 resets to a starting condition as follows:

1. All backplane outputs are set to VLCD.

2. All segment outputs are set to VLCD.

3. The drive mode ‘1 : 4 multiplex with 1⁄3 bias’ is selected.

4. Blinking is switched off.

5. Input and output bank selectors are reset (as defined in Table 7 old datasheet).

6. The I2C-bus interface is initialized.

7. The data pointer and the subaddress counter are cleared.

8. Display disabled.

You must avoid data transfers on the I2C-bus for 1 ms following power on to allow the

reset action to complete.

6.2 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider of the three

series resistors connected between VLCD and VSS. The centre resistor can be switched

out of the circuit to provide a 1⁄2 bias voltage level for the 1:2 multiplex configuration.

6.3 LCD voltage selector

The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by

MODE SET commands from the command decoder.

The biasing configurations that apply to the preferred modes of operation, together with

the biasing characteristics as functions of VOP and the resulting discrimination ratios (D),

are shown in Table 5.

PCF8534_0

Preliminary datasheet

Rev. 00.05 — 20 February 2007

© NXP B.V. 2007. All rights reserved.

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