PCF85103C-2(2002) データシートの表示（PDF） - Philips Electronics
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PCF85103C-2 Datasheet PDF : 20 Pages
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Philips Semiconductors
PCF85103C-2
256 × 8-bit CMOS EEPROM with I2C-bus interface
11. I2C-bus characteristics
Table 7: I2C-bus characteristics
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH
with an input voltage swing from VSS to VDD; see Figure 9.
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
clock frequency
tBUF
bus free time between a STOP and
START condition
0
100
kHz
4.7
−
µs
tHD;STA
START condition hold time after
which first clock pulse is generated
4.0
−
µs
tLOW
tHIGH
tSU;STA
LOW level clock period
HIGH level clock period
set-up time for START condition
repeated start
4.7
−
µs
4.0
−
µs
4.7
−
µs
tHD;DAT
data hold time
for bus compatible masters
5
−
µs
for bus devices
[1]
0
−
ns
tSU;DAT
tr
tf
tSU;STO
data set-up time
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
250
−
ns
−
1
µs
−
300
ns
4.0
−
µs
[1] The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
SDA
t BUF
t LOW
SCL
P
S
t HD;STA
tr
t HD;DAT
P = STOP condition; S = START condition.
Fig 9. Timing requirements for the I2C-bus.
tf
t HIGH
t SU;DAT
t HD;STA
S
t SU;STA
MBA705
P
t SU;STO
9397 750 09646
Product data
Rev. 02 — 09 May 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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