PC85133-1 データシートの表示（PDF） - NXP Semiconductors.
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PC85133-1 Datasheet PDF : 53 Pages
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NXP Semiconductors
PCF85133
Universal LCD driver for low multiplex rates
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Fig 4. Typical system configuration
The host microcontroller maintains the 2-line I2C-bus communication channel with the
PCF85133. The internal oscillator is enabled by connecting pin OSC to pin VSS. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are the power supplies (VDD,
VSS, and VLCD) and the LCD panel chosen for the application.
7.1 Power-on reset
At power-on the PCF85133 resets to the following starting conditions:
• All backplane and segment outputs are set to VLCD
• The selected drive mode is 1:4 multiplex with 1⁄3 bias
• Blinking is switched off
• Input and output bank selectors are reset
• The I2C-bus interface is initialized
• The data pointer and the subaddress counter are cleared (set to logic 0)
• The display is disabled (bit E = 0, see Table 12)
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between pins VLCD and VSS. The center impedance is bypassed
by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is
selected.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
PCF85133
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 4 July 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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