PC8564A-1(2010) データシートの表示（PDF） - NXP Semiconductors.

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PC8564A-1
(Rev.:2010)

Real time clock and calendar

NXP Semiconductors. 

NXP Semiconductors

PCF8564A

Real time clock and calendar

8.3.2.1 Interrupt output

Bits TF and AF: When an alarm occurs, AF is set to 1. Similarly, at the end of a timer

countdown, TF is set to 1. These bits maintain their value until overwritten using the

interface. If both timer and alarm interrupts are required in the application, the source of

the interrupt can be determined by reading these bits. To prevent one flag being

overwritten while clearing another, a logic AND is performed during a write access.

TE

COUNTDOWN COUNTER

TF: TIMER

SET

CLEAR

to interface:

read TF

PULSE

GENERATOR 2

TRIGGER

TI_TP

0

1

from interface:

clear TF

set alarm

flag AF

from interface:

clear AF

AF: ALARM

FLAG

SET

CLEAR

CLEAR

to interface:

read AF

When bits TIE and AIE are disabled, pin INT will remain high-impedance.

Fig 4. Interrupt scheme

e.g. AIE

TIE

0

1

INT

AIE

013aaa087

Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when

TF or AF is asserted respectively. The interrupt is the logical OR of these two conditions

when both AIE and TIE are set.

Countdown timer interrupts: The pulse generator for the countdown timer interrupt uses

an internal clock and is dependent on the selected source clock for the countdown timer

and on the countdown value n. As a consequence, the width of the interrupt pulse varies

(see Table 7).

Table 7. INT operation (bit TI_TP = 1)[1]

Source clock (Hz)

INT period (s)

n = 1[2]

4 096

64

1

1⁄60

1⁄8 192

1⁄128

1⁄64

1⁄64

[1] TF and INT become active simultaneously.

[2] n = loaded countdown value. Timer is stopped when n = 0.

n>1

1⁄4 096

1⁄64

1⁄64

1⁄64

PCF8564A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 02 — 30 September 2010

© NXP B.V. 2010. All rights reserved.

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