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PCF8577CT/3,118 データシートの表示(PDF) - NXP Semiconductors.

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PCF8577CT/3,118
NXP
NXP Semiconductors. NXP
PCF8577CT/3,118 Datasheet PDF : 33 Pages
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NXP Semiconductors
PCF8577C
LCD direct/duplex driver with I²C-bus interface
The control register also has two display control bits. These bits are named MODE and
BANK. The MODE bit selects whether the display outputs are configured for direct or
duplex drive displays. The BANK bit allows the user to display BANK A or BANK B.
7.4 Auto-incremented loading
After each segment byte is loaded, the SBV is incremented automatically. Thus
auto-incremented loading occurs if more than one segment byte is received in a data
transfer.
Since the SBV addresses both device and segment registers in all addressed chips,
auto-incremented loading may proceed across device boundaries if the hardware
subaddresses are arranged contiguously.
7.5 Direct drive mode
The PCF8577C is set to the direct drive mode by loading the MODE control bit with
logic 0. In this mode, only four bytes are required to store the data for the 32 segment
drivers. Setting the BANK bit to logic 0 selects even bytes (BANK A), setting the BANK bit
to logic 1 selects odd bytes (BANK B).
In the direct drive mode, the SBV is auto-incremented by two after the loading of each
segment byte register. This means, that auto-incremented loading of BANK A or BANK B
is possible. Either bank may be completely or partially loaded irrespective of which bank is
being displayed. Direct drive output waveforms are shown in Figure 4.
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Von(RMS) = VDD VSS; Voff(RMS) = 0.
Fig 4. Direct drive mode display output waveforms
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7.6 Duplex mode
The PCF8577C is set to the duplex mode by loading the MODE bit with logic 1. In this
mode, a second backplane signal (BP2) is needed and pin A2/BP2 is used for this;
therefore A2 and its equivalent SBV bit V5 are undefined. The SBV auto-increments by
one between loaded bytes.
All of the segment bytes are required to store data for the 32 segment drivers and the
BANK bit is ignored.
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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