PCF8598C-2T/02 データシートの表示（PDF） - NXP Semiconductors.
部品番号
コンポーネント説明
メーカー
PCF8598C-2T/02 Datasheet PDF : 21 Pages
| |||
Philips Semiconductors
PCF8598C-2
1024 × 8-bit CMOS EEPROM with I2C-bus interface
Table 7: Characteristics…continued
VDD = 2.5 to 6.0 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
SDA input/output (pin 5)
VIL
LOW level input voltage
−0.8
-
VIH
HIGH level input voltage
0.7VDD
-
VOL
LOW level output voltage
IOL = 3 mA; VDD(min)
-
-
ILO
output leakage current
VOH = VDD
-
-
Ci
input capacitance
VI = VSS
-
-
Data retention time
tS
data retention time
Tamb = 55 °C
10
−
11. I2C-bus characteristics
Max
0.3VDD
+6.5
0.4
1
7
−
Unit
V
V
V
µA
pF
years
Table 8: I2C-bus characteristics
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH
with an input voltage swing from VSS to VDD; see Figure 9.
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
clock frequency
tBUF
bus free time between a STOP and
START condition
0
100
kHz
4.7
−
µs
tHD;STA
START condition hold time after
which first clock pulse is generated
4.0
−
µs
tLOW
tHIGH
tSU;STA
LOW level clock period
HIGH level clock period
set-up time for START condition
repeated start
4.7
−
µs
4.0
−
µs
4.7
−
µs
tHD;DAT
data hold time
for bus compatible masters
5
−
µs
for bus devices
[1]
0
−
ns
tSU;DAT
tr
tf
tSU;STO
data set-up time
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
250
−
ns
−
1
µs
−
300
ns
4.0
−
µs
[1] The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
9397 750 14219
Product data
Rev. 06 — 22 October 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 21
Share Link: 