PCK2001M データシートの表示（PDF） - Philips Electronics
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PCK2001M Datasheet PDF : 13 Pages
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Philips Semiconductors
14.318–150 MHz I2C 1:10 Clock Buffer
Product specification
PCK2001M
AC CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
NOTES
LIMITS
Tamb = 0°C to +70°C
MIN
TYP9
MAX
UNIT
TSDKP
TSDKH
TSDKL
TSDKP
TSDKH
TSDKL
TSDKP
TSDKH
TSDKL
TSDRISE
TSDFALL
TPLH
TPHL
TPZL, TPZH
TPLZ, TPHZ
DUTY CYCLE
SDRAM CLK period
SDRAM CLK HIGH time
SDRAM CLK LOW time
SDRAM CLK period
SDRAM CLK HIGH time
SDRAM CLK LOW time
SDRAM CLK period
SDRAM CLK HIGH time
SDRAM CLK LOW time
SDRAM rise time
SDRAM fall time
SDRAM buffer LH propagation delay
SDRAM buffer HL propagation delay
SDRAM buffer enable time
SDRAM buffer disable time
Output Duty Cycle
66MHz
100MHz
133MHz
Measured at 1.5V
1, 6
2, 6, 8
3, 6, 8
1, 6
2, 6, 8
3, 6, 8
1, 6
2, 6, 8
3, 6, 8
4, 6, 10
4, 6, 11
6, 7
6, 7
6, 7
6, 7
5, 6, 7
15.0
5.6
5.3
10.0
3.3
3.1
7.4
2.6
2.1
1.5
1.5
1.0
1.0
1.0
1.0
45
15.2
7.8
7.4
10.01
5.1
4.9
7.5
3.2
2.8
2.0
2.9
2.5
2.5
2.6
2.7
52
15.5
8.4
8.0
10.5
5.7
5.5
7.7
3.8
3.5
4.0
4.0
3.5
3.5
5.0
5.0
55
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
%
TSDSKW
SDRAM Bus CLK skew
1, 6
150
250
ps
TDDSKW
Device to device skew
250
ps
NOTES:
1. Clock period and skew are measured on the rising edge at 1.5V.
2. TSDKH is measured at 2.4V as shown in Figure 4.
3. TSDKL is measured at 0.4V as shown in Figure 4.
4. TSDRISE and TSDFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V (1mA) JEDEC specification.
5. Duty cycle should be tested with a 50/50% input.
6. Over MIN (20pF) to MAX (30pF) discrete load, process, voltage, and temperature.
7. Input edge rate for these tests must be faster than 1 V/ns.
8. Calculated at minimum edge rate (1.5ns) to guarantee 45/55% duty cycle at 1.5V. Pulsewidth is required to be wider at the faster edge to
ensure duty cycle specification is met.
9. All typical values are at VCC = 3.3V and Tamb = 25°C.
10. Typical is measured with MAX (30pf) discrete load.
11. Typical is measured with MIN (20pf) discrete load.
1999 Jul 06
7
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