PCK953BD データシートの表示（PDF） - NXP Semiconductors.
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PCK953BD Datasheet PDF : 15 Pages
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NXP Semiconductors
PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
VL
=
3.0
1----8----+-----21---54----+-----2---5--
=
3.0
25----57-
=
1.31 V
(2)
At the load end, the voltage will double due to the near unity reflection coefficient, to
2.62 V. It will then increment towards the quiescent 3.0 V in steps separated by one
round-trip delay (in this case, 4.0 ns).
3.0
voltage
(V)
2.0
IN
1.0
002aae141
OutA
td = 3.8956 ns
OutB
td = 3.9386 ns
0
−0.5
0
4
8
12
16
time (ns)
Fig 5. Single versus dual waveforms
Since this step is well above the threshold region, it will not cause any false clock
triggering, however, designers may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving multiple lines, the situation in Figure 6
should be used. In this case, the series terminating resistors are reduced such that when
the parallel combination is added to the output buffer impedance, the line impedance is
perfectly matched.
PCK953
OUTPUT BUFFER
Rs = 22 Ω Zo = 50 Ω
Ro
IN
14 Ω
Rs = 22 Ω Zo = 50 Ω
002aae142
Fig 6.
14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω
25 Ω = 25 Ω
Optimized dual line termination
SPICE level output buffer models are available for engineers who want to simulate their
specific interconnect schemes. In addition, IV characteristics are in the process of being
generated to support the other board-level simulators in general use.
PCK953_5
Product data sheet
Rev. 05 — 9 October 2008
© NXP B.V. 2008. All rights reserved.
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