EK4259-02 データシートの表示（PDF） - Peregrine Semiconductor
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EK4259-02 Datasheet PDF : 11 Pages
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PE4259
Product Specification
Figure 3. Pin Configuration (Top View)
Table 2. Pin Descriptions
Pin
Pin
No.
Name
Description
1
RF11
RF Port1
Ground connection. Traces should be
2
GND
physically short and connected to ground
plane for best performance.
3
RF21
RF Port2
4
CTRL
Switch control input, CMOS logic level.
5
RFC1
RF Common
This pin supports two interface options:
Single-pin control mode. A nominal 3-volt
supply connection is required.
6
CTRL or
VDD
Complementary-pin control mode. A
complementary CMOS control signal to
CTRL is supplied to this pin. Bypassing
on this pin is not required in this mode.
Note 1: All RF pins must be DC blocked with an external series capacitor or
held at o VDC
Table 3. Operating Ranges
Parameter
VDD Power Supply
Voltage
IDD Power Supply Current
(VDD = 3V, VCNTL = 3V)
Control Voltage High
Control Voltage Low
Min
1.8
0.7x VDD
Typ Max Units
3.0
3.3
V
9
20
µA
V
0.3x VDD V
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE4259 in
the SC70 package is MSL1.
Switching Frequency
The PE4259 has a maximum 25 kHz switching rate.
Document No. 70-0134-10 │ www.psemi.com
Table 4. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD
Power supply voltage
-0.3 4.0
V
VI
Voltage on any DC input
-0.3
VDD+
0.3
V
TST
Storage temperature
range
-65 150
°C
TOP
Operating temperature
range
-40 85
°C
PIN
VESD
Input power (50 Ω)
ESD Voltage (HBM,
ML_STD 883 Method
3015.7)
ESD Voltage (MM,
JEDEC, JESD22-A114-B)
+341 dBm
2000
V
100
V
Note 1: To maintain optimum device performance, do not exceed Max PIN at
desired operating frequency (see Figure 4).
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Figure 4. Maximum Input Power
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating.
©2005-2012 Peregrine Semiconductor Corp. All rights reserved.
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