PE9311-00(2005) データシートの表示（PDF） - Peregrine Semiconductor Corp.
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PE9311-00
(Rev.:2005)
(Rev.:2005)
Peregrine Semiconductor Corp.
PE9311-00 Datasheet PDF : 7 Pages
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Figure 3. Pin Configuration
VDD
1
IN
2
N/C
3
GND 4
PE9311
8 GND
7 OUT
6 NC
5 GND
Table 2. Pin Descriptions
Pin No.
1
2
3
4
5
Pin
Name
VDD
IN
NC
GND
GND
Description
Power supply pin. Bypassing is required
(eg 1000 pF & 100 pF).
Input signal pin. Should be coupled with a
capacitor (eg 1000 pF).
No connection. This pin should be left
open.
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
Ground pin.
6
NC No connection. This pin should be left
open.
7
OUT Divided frequency output pin. This pin
should be coupled with a capacitor
(eg 1000 pF).
8
GND Ground Pin.
Table 3. Absolute Maximum Ratings
Symbol
VDD
Pin
VIN
Parameter/Conditions
Supply voltage
Input Power
Voltage on input
Min Max Units
4.0
V
15 dBm
-0.3 VDD
V
TST
Storage temperature range -65 150 °C
TOP
Operating temperature
-40 85
°C
VESD
ESD voltage (Human Body 1000
V
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
PE9311
Product Specification
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Device Functional Considerations
The PE9311 divides an input signal, up to a
frequency of 1500 MHz, by a factor of two thereby
producing an output frequency at half the input
frequency. To work properly at higher frequency,
the input and output signals (pins 2 & 7) must be
AC coupled via an external capacitor, as shown in
the test circuit in Figure 7. The input may be DC
coupled for low frequency operation with care
taken to remain within the specified DC input
range for the device.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 7 for a layout example.
Document No. 70-0114-02 │ UltraCMOS™ RFIC Solutions
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