HT48R06A-1(2000) データシートの表示（PDF） - Holtek Semiconductor

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HT48R06A-1
(Rev.:2000)

8-Bit OTP Microcontroller

Holtek Semiconductor 

Preliminary

HT48R06A-1

All of the data memory areas can handle arith-

metic, logic, increment, decrement and rotate

operations directly. Except for some dedicated

bits, each bit in the data memory can be set and

reset by "SET [m].i" and "CLR [m].i". They are

also indirectly accessible through memory

pointer register (MP;01H).

Indirect addressing register

Location 00H is an indirect addressing register

that is not physically implemented. Any

read/write operation of [00H] accesses data mem-

ory pointed to by MP (01H). Reading location 00H

itself indirectly will return the result 00H. Writ-

ing indirectly results in no operation.

The memory pointer register MP (01H) is a 7-bit

register. The bit 7 of MP is undefined and reading

will return the result 1 . Any writing operation

to MP will only transfer the lower 7-bit data to

MP.

Accumulator

The accumulator is closely related to ALU oper-

ations. It is also mapped to location 05H of the

data memory and can carry out immediate data

operations. The data movement between two

data memory locations must pass through the

accumulator.

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic

operations. The ALU provides the following func-

tions:

Arithmetic operations (ADD, ADC, SUB, SBC,

DAA)

· Logic operations (AND, OR, XOR, CPL) Rota-

tion (RL, RR, RLC, RRC)

· Increment and Decrement (INC, DEC)

· Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data op-

eration but also changes the status register.

Status register - STATUS

This 8-bit register (0AH) contains the zero flag

(Z), carry flag (C), auxiliary carry flag (AC),

overflow flag (OV), power down flag (PD), and

00H

In d ir e c t A d d r e s s in g R e g is te r

01H

MP

02H

03H

04H

05H

ACC

06H

PCL

07H

TB LP

08H

TB LH

09H

W D TS

0A H

STATU S

0B H

IN T C

0C H

S p e c ia l P u r p o s e

D ATA M EM O R Y

0D H

TM R

0E H

TM R C

0FH

10H

11H

12H

PA

13H

PAC

14H

PB

15H

PBC

16H

PC

17H

PCC

18H

19H

:U nused

1A H

R e a d a s "0 0 "

1B H

1C H

1D H

1E H

1FH

20H

3FH

40H

G e n e ra l P u rp o s e

D ATA M EM O R Y

(6 4 B y te s )

7FH

RAM mapping

watchdog time-out flag (TO). It also records the

status information and controls the operation

sequence.

With the exception of the TO and PD flags,

bits in the status register can be altered by

instructions like most other registers. Any

data written into the status register will not

change the TO or PD flag. In addition opera-

9

February 25, 2000

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