PEB20542 データシートの表示（PDF） - Infineon Technologies
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PEB20542 Datasheet PDF : 300 Pages
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PEB 20542
PEF 20542
List of Figures
Page
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HDLC Receive Data Processing in Address Mode 2 (16 bit). . . . . . . . 90
HDLC Receive Data Processing in Address Mode 2 (8 bit). . . . . . . . . 90
HDLC Receive Data Processing in Address Mode 1 . . . . . . . . . . . . . . 90
HDLC Receive Data Processing in Address Mode 0 . . . . . . . . . . . . . . 91
SCC Transmit Data Flow (HDLC Modes) . . . . . . . . . . . . . . . . . . . . . . 92
PPP Mapping/Unmapping Example. . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Asynchronous Character Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Out-of-Band DTE-DTE Bi-directional Flow Control . . . . . . . . . . . . . . 105
Out-of-Band DTE-DCE Bi-directional Flow Control . . . . . . . . . . . . . . 106
BISYNC Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Processing of Received Frames in Auto Mode . . . . . . . . . . . . . . . . . 111
Timer Procedure/Poll Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Transmission/Reception of I-Frames and Flow Control . . . . . . . . . . . 114
Flow Control: Reception of S-Commands and Protocol Errors . . . . . 114
No Data to Send: Data Reception/Transmission . . . . . . . . . . . . . . . . 117
Data Transmission (without error), Data Transmission (with error) . . 117
Interrupt Driven Data Transmission (Flow Diagram) . . . . . . . . . . . . . 260
Interrupt Driven Data Reception (Flow Diagram) . . . . . . . . . . . . . . . . 262
DMA Transmit (Single Buffer per Packet) . . . . . . . . . . . . . . . . . . . . . 264
Fragmented DMA Transmission (Multiple Buffers per Packet) . . . . . 265
DMA Controlled Data Transmission (Flow Diagram) . . . . . . . . . . . . . 266
DMA Receive (Single Buffer per Packet) . . . . . . . . . . . . . . . . . . . . . . 267
Fragmented Reception per DMA (Example) . . . . . . . . . . . . . . . . . . . 268
Fragmented Reception Sequence (Example) . . . . . . . . . . . . . . . . . . 269
DMA Controlled Data Reception (Flow Diagram) . . . . . . . . . . . . . . . 270
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 274
Microprocessor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 276
Infineon/Intel Read Cycle Timing (Slave Access) . . . . . . . . . . . . . . . 277
Infineon/Intel Write Cycle Timing (Slave Access) . . . . . . . . . . . . . . . 277
Motorola Read Cycle Timing (Slave Access). . . . . . . . . . . . . . . . . . . 279
Motorola Write Cycle Timing (Slave Access) . . . . . . . . . . . . . . . . . . . 279
Infineon/Intel Read Cycle Timing (Master Access) . . . . . . . . . . . . . . 281
Infineon/Intel Write Cycle Timing (Master Access) . . . . . . . . . . . . . . 282
Motorola Read Cycle Timing (Master Access). . . . . . . . . . . . . . . . . . 283
Motorola Write Cycle Timing (Master Access) . . . . . . . . . . . . . . . . . . 284
Bus Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Clock Mode 1 Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Clock Mode 4 Receive Gating Timing . . . . . . . . . . . . . . . . . . . . . . . . 291
Clock Mode 4 Transmit Gating Timing. . . . . . . . . . . . . . . . . . . . . . . . 291
Data Sheet
10
2000-09-14
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