PG001 データシートの表示（PDF） - Allegro MicroSystems

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PG001

PARALLEL-TO-SERIAL DATA CONVERTER

Allegro MicroSystems 

PG001M

PARALLEL-TO-SERIAL

DATA CONVERTER

RESET

CLOCK

IN

CCW/CW

MODE

SELECT1

MODE

SELECT 2

1/4-STEP MODE

VECTOR

CONTROL

CLOCK

OUT

71.4

40

0

SERIAL

DATA A

40

71.4

71.4

91

100

91

71.4

SERIAL

DATAB

STROBE

MONITOR

FULL-STEP MODE

71.4

71.4

71.4

71.4

FULL-STEP MODE

MAXIMUM TORQUE

(141%)

100

100

PER CENT

OUT A

PER CENT

OUT B

71.4

40

FIRST QUADRANT

71.4

91

0

-40

100

91

-71.4

SECOND QUADRANT

71.4

-71.4

THIRD QUADRANT

-71.4

71.4

FOURTH QUADRANT

-71.4

Figure 4 — Quarter-Step, Full-Step, and High-Torque Full-Step

100

FIRST QUADRANT

100

Dwg. WK-006

Because the parallel-to-serial conversion requires six

'static' logic signals plus a 'dynamic' (clock) input, the

addition of latches between the µP and five of the control-

ler IC inputs permits use on a bus. Latching the five

signals to CCW/CW, MS1, MS2 , RESET, and VC frees

these five I/O lines for other operations by the

microcontroller. Even at extremely high step rates (>5

kHz), updating the PG001M input data requires an infini-

tesimal percentage of the µP's I/O and control operations.

115 Northeast Cutoff, Box 15036

™

Worcester, Massachusetts 01615-0036 (508) 853-5000

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