A6275EA データシートの表示（PDF） - Allegro MicroSystems

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A6275EA

8-Bit Serial Input Constant-Current Latched LED Driver

Allegro MicroSystems 

A6275

Serial-Input Constant-Current Latched LED Driver

with Open LED Detection and Dot Correction

Applications Information

The load current per bit (IO) is set by the external resistor

(REXT) as shown in the figure below.

100

V CE = 0.7 V

80

60

40

20

0

100

200 300

500 700 1 k

CURRENT-CONTROL RESISTANCE, R

2k 3k

5k

EXT IN OHMS

Dwg. GP-061

Package Power Dissipation (PD). The maximum al-

lowable package power dissipation is determined as

PD(max) = (150 - TA)/RθJA.

The actual package power dissipation is

PD(act) = dc(VCE × IO × 8) + (VDD × IDD).

When the load supply voltage is greater than 3 V to 5 V,

considering the package power dissipating limits of these

devices, or if PD(act) > PD(max), an external voltage re-

ducer (VDROP) should be used.

Load Supply Voltage (VLED). These devices are de-

signed to operate with driver voltage drops (VCE) of

0.4 V to 0.7 V with LED forward voltages (VF) of 1.2 V to

4.0 V. If higher voltages are dropped across the driver,

package power dissipation will be increased significantly.

To minimize package power dissipation, it is recom-

mended to use the lowest possible load supply voltage or

to set any series dropping voltage (VDROP) as

VDROP = VLED - VF - VCE

with VDROP = Io × RDROP for a single driver, or a Zener

diode (VZ), or a series string of diodes (approximately

0.7 V per diode) for a group of drivers. If the available

voltage source will cause unacceptable dissipation and

series resistors or diode(s) are undesirable, a regulator

such as the Sanken Series SAI or Series SI can be used to

provide supply voltages as low as 3.3 V.

For reference, typical LED forward voltages are:

White

3.5 – 4.0 V

Blue

3.0 – 4.0 V

Green

1.8 – 2.2 V

Yellow

2.0 – 2.1 V

Amber

1.9 – 2.65 V

Red

1.6 – 2.25 V

Infrared

1.2 – 1.5 V

Pattern Layout. This device has a common logic-ground

and power-ground terminal. If ground pattern layout

contains large common-mode resistance, and the voltage

between the system ground and the LATCH ENABLE or

CLOCK terminals exceeds 2.5 V (because of switching

noise), these devices may not operate correctly.

V LED

V DROP

VF

V CE

Dwg. EP-064

Allegro MicroSystems, Inc.

10

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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