SN74LS322AN データシートの表示（PDF） - Motorola => Freescale
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SN74LS322AN Datasheet PDF : 4 Pages
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SN54 / 74LS322A
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
fMAX
Maximum Clock Frequency
25
35
tPHL
tPLH
Propagation Delay, Clock
to QH′
26
35
22
33
tPHL
Propagation Delay, Clear
to QH′
27
35
tPHL
tPLH
Propagation Delay, Clock
to QA– QH
22
33
16
25
tPHL
Propagation Delay, Clear
to QA– QH
22
35
tPZH
tPZL
Output Enable Time
15
35
15
35
tPHZ
tPLZ
Output Disable Time
15
25
15
25
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
tW
Clock Pulse Width HIGH
25
tW
Clock Pulse Width LOW
15
tW
Clear Pulse Width LOW
20
ts
Data Setup Time
20
ts
Select Setup Time
15
th
Data Hold Time
0
th
Select Hold Time
10
trec
Recovery Time
20
Unit
MHz
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
CL = 15 pF
CL = 45 pF,
RL = 667 Ω
CL = 5.0 pF
Test Conditions
VCC = 5.0 V
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
FAST AND LS TTL DATA
5-4
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