CF745 データシートの表示（PDF） - Microchip Technology

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CF745

EPROM/ROM-Based 8-Bit CMOS Microcontroller Series

Microchip Technology 

PIC16C5X

5.0 I/O PORTS

As with any other register, the I/O registers can be

written and read under program control. However, read

instructions (e.g., MOVF PORTB,W) always read the I/O

pins independent of the pin’s input/output modes. On

RESET, all I/O ports are defined as input (inputs are at

hi-impedance) since the I/O control registers (TRISA,

TRISB, TRISC) are all set.

5.1 PORTA

PORTA is a 4-bit I/O register. Only the low order 4 bits

are used (RA3:RA0). Bits 7-4 are unimplemented and

read as '0's.

5.2 PORTB

PORTB is an 8-bit I/O register (PORTB<7:0>).

5.3 PORTC

PORTC is an 8-bit I/O register for PIC16C55s,

PIC16C57s and PIC16CR57s.

PORTC is a general purpose register for PIC16C52,

PIC16C54s, PIC16CR54s, PIC16C56s, PIC16C58s

and PIC16CR58s.

5.4 TRIS Registers

The output driver control registers are loaded with the

contents of the W register by executing the TRIS f

instruction. A '1' from a TRIS register bit puts the

corresponding output driver in a hi-impedance mode.

A '0' puts the contents of the output data latch on the

selected pins, enabling the output buffer.

Note:

A read of the ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but the external system is holding it low, a

read of the port will indicate that the pin is

low.

The TRIS registers are “write-only” and are set (output

drivers disabled) upon RESET.

5.5 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in

Figure 5-1. All ports may be used for both input and

output operation. For input operations these ports are

non-latching. Any input must be present until read by

an input instruction (e.g., MOVF PORTB, W). The

outputs are latched and remain unchanged until the

output latch is rewritten. To use a port pin as output,

the corresponding direction control bit (in TRISA,

TRISB) must be cleared (= 0). For use as an input, the

corresponding TRIS bit must be set. Any I/O pin can

be programmed individually as input or output.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Data

Bus

D

Q

Data

WR

Latch

VDD

Port

CK Q

P

W

Reg

TRIS ‘f’

D

Q

TRIS

Latch

CK Q

N

I/O

pin(1)

VSS

Reset

RD Port

Note 1: I/O pins have protection diodes to VDD and VSS.

TABLE 5-1: SUMMARY OF PORT REGISTERS

Address

Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

N/A

TRIS

I/O control registers (TRISA, TRISB, TRISC)

05h

PORTA

—

—

—

—

RA3

06h

PORTB

RB7 RB6 RB5 RB4 RB3

07h

PORTC

RC7 RC6 RC5 RC4 RC3

Legend: Shaded boxes = unimplemented, read as ‘0’,

– = unimplemented, read as '0', x = unknown, u = unchanged

RA2

RB2

RC2

Bit 1

RA1

RB1

RC1

Bit 0

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

RA0

RB0

RC0

1111 1111 1111 1111

---- xxxx ---- uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

© 1998 Microchip Technology Inc.

Preliminary

DS30453B-page 25

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