CF745 データシートの表示（PDF） - Microchip Technology

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CF745

EPROM/ROM-Based 8-Bit CMOS Microcontroller Series

Microchip Technology 

PIC16C5X

6.0 TIMER0 MODULE AND

TMR0 REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0

module, while Figure 6-2 shows the electrical structure

of the Timer0 input.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 6-3 and Figure 6-4).

The user can work around this by writing an adjusted

value to the TMR0 register.

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on every rising or falling edge of pin T0CKI. The

incrementing edge is determined by the source edge

select bit T0SE (OPTION<4>). Clearing the T0SE bit

selects the rising edge. Restrictions on the external

clock input are discussed in detail in Section 6.1.

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit PSA (OPTION<3>). Clearing the PSA bit

will assign the prescaler to Timer0. The prescaler is

not readable or writable. When the prescaler is

assigned to the Timer0 module, prescale values of 1:2,

1:4,..., 1:256 are selectable. Section 6.2 details the

operation of the prescaler.

A summary of registers associated with the Timer0

module is found in Table 6-1.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

FOSC/4

T0CKI

pin

T0SE(1)

Data bus

0

PSout

8

1

Sync with

1

Internal

TMR0 reg

Programmable

Prescaler(2)

0

Clocks

PSout

(2 cycle delay) Sync

T0CS(1)

3

PS2, PS1, PS0(1)

PSA(1)

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-6).

FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN

RIN

T0CKI

(1)

pin

(1)

N

Schmitt Trigger

Input Buffer

VSS

VSS

Note 1: ESD protection circuits

© 1998 Microchip Technology Inc.

Preliminary

DS30453B-page 27

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