PIC16C432(2002) データシートの表示（PDF） - Microchip Technology

部品番号

コンポーネント説明

メーカー

PIC16C432
(Rev.:2002)

OTP 8-Bit CMOS MCU with LIN Transceiver

Microchip Technology 

PIC16C432

TABLE 3-1: SPECIAL REGISTERS FOR THE PIC16C432

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR Reset

Value on all

other

RESETS(1)

Bank 0

00h

INDF

01h

TMR0

02h

PCL

03h

STATUS

04h

FSR

05h

PORTA

06h

PORTB

07h

—

08h

—

09h

—

0Ah

PCLATH

0Bh

INTCON

0Ch

PIR1

0Dh-1Eh —

1Fh

CMCON

Bank 1

80h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical

xxxx xxxx

16

register)

Timer0 Module’s Register

xxxx xxxx

27

Program Counter's (PC) Least Significant Byte

0000 0000

15

IRP(2)

RP1(2)

RP0

TO

PD

Z

DC

C

0001 1xxx

10

Indirect data memory address pointer

xxxx xxxx

16

—

—

—

RA4

RA3

RA2

LINRX

RA0 ---x 0000

17

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0 xxxx xxxx

20

Unimplemented

—

—

Unimplemented

—

—

Unimplemented

—

—

—

—

— Write buffer for upper 5 bits of program counter

---0 0000

15

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF 0000 000x

12

—

CMIF

—

—

—

—

—

—

-0-- ----

13

Unimplemented

—

—

C2OUT C1OUT

—

—

CIS

CM2

CM1

CM0 00-- 0000

33

Addressing this location uses contents of FSR to address data memory (not a physical

xxxx xxxx

16

register)

81h

OPTION_REG RBPU INTEDG T0CS T0SE

PSA

PS2

PS1

PS0 1111 1111

11

82h

PCL

Program Counter's (PC) Least Significant Byte

0000 0000

15

83h

STATUS

84h

FSR

85h

TRISA

86h

TRISB

87h

—

88h

—

89h

—

8Ah

PCLATH

8Bh

INTCON

8Ch

PIE1

8Dh

—

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx

10

Indirect data memory address pointer

xxxx xxxx

16

—

—

—

TRISA4 TRISA3 TRISA2 TLINRX(3) TRISA0 ---1 1111

17

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111

20

Unimplemented

—

—

Unimplemented

—

—

Unimplemented

—

—

—

—

—

Write buffer for upper 5 bits of program counter

---0 0000

15

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF 0000 000x

12

—

CMIE

—

—

—

—

—

—

-0-- ----

13

Unimplemented

—

—

8Eh

PCON

—

—

—

—

—

—

POR

BOD ---- --0x

14

8Fh-9Eh —

Unimplemented

—

—

90h

LININTF

—

—

—

—

—

LINTX

—

LINVDD ---- -1-1

23

9Fh

VRCON

VREN VROE VRR

—

VR3

VR2

VR1

VR0 000- 0000

41

Legend:

Note 1:

2:

3:

— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Other (non power-up) RESETS include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation.

IRP & RPI bits are reserved; always maintain these bits clear.

TLINRX must set to ‘1’ at all times.

 2002 Microchip Technology Inc.

Preliminary

DS41140B-page 9

Share Link: