ISPLSI5384VA-125LB208I(2000) データシートの表示（PDF） - Lattice Semiconductor

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ISPLSI5384VA-125LB208I
(Rev.:2000)

In-System Programmable 3.3V SuperWIDE™ High Density PLD

Lattice Semiconductor 

Specifications ispLSI 5384VA

Figure 8. Boundary Scan Waveforms and Timing Specifications

TMS

TDI

TCK

Tbtch

Tbtsu

Tbtcl

Tbth

Tbtcp

TDO

Data to be

captured

Data to be

driven out

Tbtvo

Tbtco

Valid Data

Tbtcpsu

Tbtcph

Data Captured

Tbtuov

Tbtuco

Valid Data

Tbtoz

Valid Data

T btuoz

Valid Data

SYMBOL PARAMETER

tbtcp

tbtch

tbtcl

tbtsu

tbth

trf

tbtco

tbtoz

tbtvo

tbtcpsu

tbtcph

tbtuco

tbtuoz

tbtuov

TCK [BSCAN test] clock pulse width

TCK [BSCAN test] pulse width high

TCK [BSCAN test] pulse width low

TCK [BSCAN test] setup time

TCK [BSCAN test] hold time

TCK [BSCAN test] rise and fall time

TAP controller falling edge of clock to valid output

TAP controller falling edge of clock to data output disable

TAP controller falling edge of clock to data output enable

BSCAN test Capture register setup time

BSCAN test Capture register hold time

BSCAN test Update reg, falling edge of clock to valid output

BSCAN test Update reg, falling edge of clock to output disable

BSCAN test Update reg, falling edge of clock to output enable

MIN MAX UNITS

125 –

ns

62.5 –

ns

62.5 –

ns

25

–

ns

25

–

ns

50

– mV/ns

–

25 ns

–

25 ns

–

25 ns

25

–

ns

25

–

ns

–

50 ns

–

50 ns

–

50 ns

9

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