AD9283 データシートの表示（PDF） - Analog Devices
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AD9283 Datasheet PDF : 12 Pages
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AD9283–SPECIFICATIONS (VDD = 3.0 V, VD = 3.0 V; single-ended input; external reference, unless otherwise noted)
Parameter
Test AD9283BRS-100
Temp Level Min Typ Max
AD9283BRS-80
Min Typ Max
AD9283BRS-50
Min Typ Max
Unit
RESOLUTION
8
8
8
Bits
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
Gain Error1
Gain Tempco1
25°C I
Full VI
25°C I
Full VI
Full VI
25°C I
Full VI
Full VI
± 0.5
–1.25 ± 0.75
Guaranteed
–6 ± 2.5
–8
80
+1.25
+1.50
+1.25
+2.25
+6
+8
± 0.5
–1.25 ± 0.75
Guaranteed
–6 ± 2.5
–8
80
+1.25
+1.50
+1.25
+1.50
+6
+8
± 0.5
–1.25 ± 0.75
Guaranteed
–6 ± 2.5
–8
80
+1.25
+1.50
+1.25
+1.50
+6
+8
LSB
LSB
LSB
LSB
% FS
% FS
ppm/°C
ANALOG INPUT
Input Voltage Range
(With Respect to AIN)
Common-Mode Voltage
Full V
Full V
Input Offset Voltage
25°C I
Full VI
Reference Voltage
Full VI
Reference Tempco
Full VI
Input Resistance
25°C I
Full VI
Input Capacitance
25°C V
Full VI
Analog Bandwidth, Full Power 25°C V
± 512
± 200
–35 ± 10 +35
± 40
1.2 1.25 1.3
± 130
7
10 13
5
16
2
475
± 512
± 200
–35 ± 10 +35
± 40
1.2 1.25 1.3
± 130
7
10 13
5
16
2
475
± 512
± 200
–35 ± 10 +35
± 40
1.2 1.25 1.3
± 130
7
10 13
5
16
2
475
mV p-p
mV
mV
mV
V
ppm/°C
kΩ
kΩ
pF
µA
MHz
SWITCHING PERFORMANCE
Maximum Conversion Rate
Full VI
Minimum Conversion Rate
25°C IV
Encode Pulsewidth High (tEH) 25°C IV
Encode Pulsewidth Low (tEL)
25°C IV
Aperture Delay (tA)
25°C V
Aperture Uncertainty (Jitter)
25°C V
Output Valid Time (tV)2
Full VI
Output Propagation Delay (tPD)2 Full
VI
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Full VI
Full VI
Full VI
Full VI
25°C V
100
4.3
4.3
0
5
2.0 3.0
4.5
1
1000
1000
7.0
2.0
0.8
±1
±1
2.0
80
1
5.0
1000
5.0
1000
0
5
2.0 3.0
4.5 7.0
2.0
0.8
±1
±1
2.0
50
MSPS
1
MSPS
8.0
1000 ns
8.0
1000 ns
0
ns
5
ps rms
2.0 3.0
ns
4.5 7.0
ns
2.0
V
0.8
V
±1
µA
±1
µA
2.0
pF
DIGITAL OUTPUTS
Logic “1” Voltage
Logic “0” Voltage
Output Coding
Full VI 2.95
2.95
2.95
V
Full VI
0.05
0.05
0.05 V
Offset Binary Code
Offset Binary Code
Offset Binary Code
POWER SUPPLY
Power Dissipation3, 4
Power-Down Dissipation
Power Supply Rejection Ratio
(PSRR)
Full VI
Full VI
25°C I
90 120
4.2 7
18
90 115
4.2 7
18
80 100
4.2 7
18
mW
mW
mV/V
–2–
REV. C
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