PLL102-108XC データシートの表示（PDF） - PhaseLink Corporation
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PLL102-108XC Datasheet PDF : 10 Pages
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PLL102-108
Programmable DDR Zero Delay Clock Driver
TABLE 1: Output Signals SKEW Programming Summary:
Bit<2:0>
111
110
101
100
011
010
001
000
DDR Skew Setting (±100ps/step)
+400ps
+300ps
+200ps
+100ps
Default
-100ps
-200ps
-300ps
Setting applies to the following
outputs:
1. DDRA: CLK0, CLK1, CLK5
2. DDRB: CLK7, CLK8, CLK9
3. DDRC: CLK2, CLK3, CLK4
4. DDRD: CLK6
FBOUT Skew Setting (±200ps/step)
+800ps
+600ps
+400ps
+200ps
Default
-200ps
-400ps
-600ps
Setting applies to the following out-
puts:
1. FB_OUTT
2. BYTE 1: SKEW Register (1=Enable, 0=Disable)
Bit
Name
Default
Description
Bit 7
26,27
1
CLKT9, CLKC9 (1= active, 0=inactive)
Bit 6
29,30
1
CLKT8, CLKC8 (1= active, 0=inactive)
Bit 5
Bit 4
Bit 3
Skew
DDRA
Bit <2>
Bit <1>
Bit <0>
0
These three bits will adjust timing of DDRA signals (CLK0, CLK1,
1
CLK5) either positive or negative delay up to +400ps or –300ps
1
with ±100ps per step. (see Table 1)
Bit 2
Bit 1
Bit 0
Skew
DDRB
Bit <2>
Bit <1>
Bit <0>
0
These three bits will adjust timing of DDRB signals (CLK7, CLK8,
1
CLK9) either positive or negative delay up to +400ps or –300ps
1
with ±100ps per step. (see Table 1)
3. BYTE 2: SKEW Register (1=Enable, 0=Disable)
Bit
Name
Default
Description
Bit 7
DDR-SKEWEN
1
1= disable, 0= enable
Bit 6
FBOUT-SKEWEN
1
1= disable, 0= enable
Bit 5
Bit 4
Bit 3
Skew
DDRC
Bit <2>
Bit <1>
Bit <0>
0
These three bits will adjust timing of DDRC signals (CLK2, CLK3,
1
CLK4) either positive or negative delay up to +400ps or –300ps
1
with ±100ps per step. (see Table 1)
Bit 2
Bit 1
Bit 0
Skew
DDRD
Bit <2>
Bit <1>
Bit <0>
0
These three bits will adjust timing of DDRD signals (CLK6) either
1
positive or negative delay up to +400ps or –300ps with ±100ps per
1
step. (see Table 1)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/29/02 Page 4
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