PLL102-109 データシートの表示（PDF） - PhaseLink Corporation
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PLL102-109 Datasheet PDF : 10 Pages
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Preliminary PLL102-109
Programmable DDR Zero Delay Clock Driver
FEATURES
• PLL clock distribution optimized for Double Data
Rate SDRAM application up to 266Mhz.
• Distributes one clock Input to one bank of six
differential outputs.
• Track spread spectrum clocking for EMI reduction.
• Programmable delay between CLK_INT and CLK[T/C]
from –0.8ns to +3.1ns by programming CLKINT and
FBOUT skew channel, or from –1.1ns to +3.5ns if
additional DDR skew channels are enabled.
• Two independent programmable DDR skew chan-
nels from –0.3ns to +0.4ns with step size ±100ps.
• Support 2-wire I2C serial bus interface.
• 2.5V Operating Voltage.
• Available in 28-Pin 209mil SSOP.
PIN CONFIGURATION
CLKCO 1
28
CLKT0 2
27
VDD 3
26
CLKT1 4
25
CLKC1 5
24
GND 6
23
SCLK 7
22
CLK_INT 8
21
N/C 9
20
AVDD 10
19
AGND 11
18
VDD 12
17
CLKT2 13
16
CLKC2 14
15
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
N/C
FB_INT
FB_OUTT
ADDR_SEL
CLKT3
CLKC3
GND
DESCRIPTIONS
The PLL102-109 is a zero delay buffer that distributes
a single-ended clock input to six pairs of differential
clock outputs and one feedback clock output. Output
signal duty cycles are adjusted to 50%, independent of
the duty cycle at CLK_INT. The PLL can be bypassed
for test purposes by strapping AVDD to ground.
BLOCK DIAGRAM
AVDD
CLK_INT
FB_INT
AV DD
Programmable
Delay Channel
(0~2.5ns)
+170ps step
Control
Logic
PLL
Programmable
Skew Channel
-600~+800ps
±200ps step
-300~+400ps
±100ps step
-300~+400ps
±100ps step
FB_OUTT
CLKT0
CLKC0
CLKT1
CLKC1
CLKT5
CLKC5
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/26/03 Page 1
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